FB IN VDDA 1:4, Differential-to-LVCMOS/LVTTL ICS87004 Zero Delay Clock Generator DATA SHEET General Description Features The ICS87004 is a highly versatile 1:4 Differential- Four LVCMOS/LVTTL outputs, 7 typical output impedance ICS to-LVCMOS/LVTTL Clock Generator and a member of Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs HiPerClockS the HiPerClockS family of High Performance Clock CLKx/nCLKx pairs can accept the following differential Solutions from IDT. The ICS87004 has two selectable input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL pairs can accept most standard differential input levels. Internal bias levels on CLK0 and CLK1 inputs on the nCLK0 and nCLK1 inputs allows the CLK0 and CLK1 inputs Output frequency range: 15.625MHz to 250MHz to accept LVCMOS/LVTTL. The ICS87004 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider and Input frequency range: 15.625MHz to 250MHz has an input and output frequency range of 15.625MHz to 250MHz. VCO range: 250MHz to 500MHz The reference divider, feedback divider and output divider are each External feedback for zero delay clock regeneration with programmable, thereby allowing for the following output-to-input configurable frequencies frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external Programmable dividers allow for the following output-to-input feedback allows the device to achieve zero delay between the input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 clock and the output clocks. The PLL SEL pin can be used to Fully integrated PLL bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the Cycle-to-cycle jitter: 45ps (maximum) internal output dividers. Output skew: 50ps (maximum) Static phase offset: 50ps 125ps (3.3V 5%), CLK0/nCLK0 Full 3.3V or 2.5V output operating supply 5V tolerant inputs 0C to 70C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Block Diagram Pin Assignment Pullup PLL SEL GND 1 24 Q1 Q0 2 23 VDDO 2, 4, 8, 16 VDDO 3 22 Q2 Q0 32, 64, 128 0 SEL0 4 21 GND Pulldown CLK0 0 Pullup/Pulldown SEL1 5 20 Q3 nCLK0 Q1 SEL2 6 19 VDDO 1 Pulldown CLK1 SEL3 7 18 MR 1 Pullup/Pulldown nCLK1 PLL CLK SEL 8 17 Q2 9 PLL SEL VDD 16 Pulldown CLK0 10 15 CLK1 CLK SEL nCLK0 11 14 nCLK1 8:1, 4:1, 2:1, 1:1, Q3 GND 12 13 Pulldown FB IN 1:2, 1:4, 1:8 ICS87004 24-Lead TSSOP 7.8mm x 4.4mm x 0.925mm package body G Package Pulldown SEL0 Top View Pulldown SEL1 Pulldown SEL2 Pulldown SEL3 Pulldown MR ICS87004AG REVISION C DECEMBER 1, 2009 1 2009 Integrated Device Technology, Inc.ICS87004 Data Sheet 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR Table 1. Pin Descriptions Number Name Type Description 1, 12, 21 GND Power Power supply ground. 2, 20, Q0, Q3, Single-ended clock outputs. 7 typical output impedance. Output 22, 24 Q2, Q1 LVCMOS/LVTTL interface levels. 3, 19, 23 V Power Output supply pins. DDO 4, 5, SEL0, SEL1, Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 6, 7 SEL2, SEL3 Clock select input. When HIGH, selects differential CLK1, nCLK1. When LOW, 8 CLK SEL Input Pulldown selects differential CLK0, nCLK0. LVCMOS/LVTTL interface levels. 9V Power Core supply pin. DD 10 CLK0 Input Pulldown Non-inverting differential clock input. Pullup/ 11 nCLK0 Input Inverting differential clock input. V /2 default when left floating. DD Pulldown 13 V Power Analog supply pin. DDA Pullup/ 14 nCLK1 Input Inverting differential clock input. V /2 default when left floating. DD Pulldown 15 CLK1 Input Pulldown Non-inverting differential clock input. PLL select. Selects between the PLL and reference clock as the input to the 16 PLL SEL Input Pullup dividers. When LOW, selects the reference clock (PLL Bypass). When HIGH, selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels. Feedback input to phase detector for regenerating clocks with Zero Delay. 17 FB IN Input Pulldown Connect to one of the outputs. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset 18 MR Input Pulldown causing the outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 4pF C IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN , V = 3.465V 23 pF V Power Dissipation DD DDO C PD Capacitance (per output) V , V = 2.625V 17 pF DD DDO R Output Impedance 5 7 12 OUT ICS87004AG REVISION C DECEMBER 1, 2009 2 2009 Integrated Device Technology, Inc.