1/2 Differential-to-LVCMOS/LVTTL 87021I Data Sheet Clock Generator GENERAL DESCRIPTION FEATURES The 87021I is a high performance 1/2 Differential-to-LVCMOS/ Two single-ended LVCMOS/LVTTL outputs LVTTL Clock Generator and a member of the family of High One differential CLK, nCLK input pair Performance Clock Solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels. Guaranteed part- CLK, nCLK pair can accept the following differential to-part skew characteristics make the 87021I ideal for those clock input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL distribution applications demanding well de ned performance Maximum output frequency: 250MHz and repeatability. Additive phase jitter, RMS: 0.18ps (typical) Output skew: 50ps (maximum) Part-to-part skew: 450ps (maximum) Propagation delay: 3.4ns (maximum) Full 3.3V or 2.5V operating supply -40C to 85C ambient operating temperature Availalbe in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT CLK VDD 1 8 1 0 nCLK 2 7 Q0 CLK Q0 nCLK MR 3 6 Q1 1 2 F SEL 4 5 GND R Q1 87021I MR 8-Lead SOIC 3.90mm x 4.90mm x 1.375mm package body M Package F SEL Top View 2grated Device Technology, Inc 1 September 2, 202187021I Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 CLK Input Pulldown Non-inverting differential clock input. 2 nCLK Input Pullup Inverting differential clock input. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the outputs to go low. When logic LOW, the internal divid- 3 MR Input Pulldown ers and the outputs are enabled. LVCMOS / LVTTL interface levels. See Table 3. Selects divider value for Qx outputs as described in Table 3. 4 F SEL Input Pulldown LVCMOS / LVTTL interface levels. 5 GND Power Power supply ground. 6 Q1 Output Singled-ended output. LVCMOS/LVTTL interface levels. 7 Q0 Output Singled-ended output. LVCMOS/LVTTL interface levels. 8V Power Positive supply pin. DD NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN V = 3.465V 24 pF Power Dissipation Capacitance DD C PD (per output) V = 2.625V 16 pF DD R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN R Output Impedance V = 3.465V 9 OUT DD 201Igrated Device Technology, Inc 2 September 2, 2021