Zero Delay, Differential-to-LVCMOS/ 8705I LVTTL Clock Generator Not Recommend for New Designs DATA SHEET GENERAL DESCRIPTION FEATURES The 8705I is a highly versatile 1:8 Differential-to-LVCMOS/ Eight LVCMOS/LVTTL outputs, 7 typical output impedance LVTTL Clock Generator. The 8705I has two selectable clock Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs inputs. The CLK1, nCLK1 pair can accept most standard CLK1, nCLK1 pair can accept the following differential differential input levels. The single ended CLK0 input accepts input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL LVCMOS or LVTTL input levels.The 8705I has a fully integrated CLK0 input accepts LVCMOS or LVTTL input levels PLL and can be con gured as zero delay buffer, multiplier or divider and has an input and output frequency range of Output frequency range: 15.625MHz to 250MHz 15.625MHz to 250MHz. The reference divider, feedback divider Input frequency range: 15.625MHz to 250MHz and output divider are each programmable, thereby allowing for VCO range: 250MHz to 500MHz the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve External feedback for zero delay clock regeneration zero delay between the input clock and the output clocks. The with con gurable frequencies PLL SEL pin can be used to bypass the PLL for system test and Programmable dividers allow for the following output-to-input debug purposes. In bypass mode, the reference clock is routed frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 around the PLL and into the internal output dividers. Fully integrated PLL Cycle-to-cycle jitter: 45ps (maximum) Output skew: CLK0, 65ps (maximum) CLK1, nCLK1, 55ps (maximum) Static Phase Offset: 25 125ps (maximum), CLK0 Full 3.3V or 2.5V operating supply Lead-Free package available -40C to 85C ambient operating temperature Not Recommended for New Designs For new designs, contact IDT. BLOCK DIAGRAM PIN ASSIGNMENT 32-Lead LQFP 7mm x 7mm x 1.4 mm Y Package Top View 8705I REVISION E 7/13/15 1 2015 Integrated Device Technology, Inc.8705I DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description Determines output divider values in Table 3. 1, 2 SEL0, SEL1 Input Pulldown LVCMOS/LVTTL interface levels. 3 CLK0 Input Pulldown Clock input. LVCMOS/LVTTL interface levels. 4 nc No connect. 5 CLK1 Input Pulldown Non-inverting differential clock input. 6 nCLK1 Input Pullup Inverting differential clock input. Clock select input. When HIGH, selects differential CLK1, nCLK1. When 7 CLK SEL Input Pulldown LOW, selects LVCMOS CLK0. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are 8 MR Input Pulldown reset causing the outputs to go low. When logic LOW, the internal divid- ers and the outputs are enabled. LVCMOS/LVTTL interface levels 9, 32 V Power Core supply pins. DD LVCMOS/LVTTL feedback input to phase detector for regenerating 10 FB IN Input Pulldown clocks with zero delay. Connect to one of the outputs. LVCMOS/LVTTL interface levels. Determines output divider values in Table 3. 11 SEL2 Input Pulldown LVCMOS/LVTTL interface levels. 12, 16, 20, 24, V Power Output supply pins. DDO 28 Q0, Q1, Q2, 13, 15, 17, 19, Clock output. 7 typical output impedance. Q3, Q4, Q5, Output 21, 23, 25, 27 LVCMOS/LVTTL interface levels. Q6, Q7 14, 18, 22, 26 GND Power Power supply ground. Determines output divider values in Table 3. 29 SEL3 Input Pulldown LVCMOS/LVTTL interface levels. 30 V Power Analog supply pin. DDA Selects between the PLL and reference clock as input to the dividers. 31 PLL SEL Input Pullup When LOW, selects the reference clock (PLL Bypass). When HIGH, selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 K PULLUP R Input Pulldown Resistor 51 K PULLDOWN Power Dissipation Capacitance C V , V , V = 3.465V 23 pF PD DD DDA DDO (per output) R Output Impedance 5 7 12 OUT Zero Delay, Differential-to-LVCMOS/ 2 REVISION E 7/13/15 LVTTL Clock Generator