Q3 VDD Q2 GND PLL EN GND Q1 LVCMOS Clock Generator 870931I-01 Data Sheet General Description Features Single-ended input reference clock The 870931I-01 is an LVCMOS clock generator that uses an internal phase lock loop (PLL) for frequency multiplication and to lock the Six single-ended clock outputs low-skew outputs to the reference clock. The device offers six Internal PLL does not require external loop filter components outputs. The PLL loop filter is completely internal and does not 5V tolerant inputs require external components. Several combinations of the PLL Maximum output frequency: 80MHz, (Q0:Q4 outputs) feedback and a divide-by-2 (controlled by FREQ SEL) allow Maximum output frequency: 40MHz, (Q/2 output) applications to optimize frequency generation over a wide range of LVCMOS interface levels for all inputs and outputs input reference frequencies. The PLL can also be disabled by the PLL disable feature for low-frequency testing PLL EN control signal to allow for low frequency or DC testing. The Output drive capability: 24mA 870931I-01 device is a member of the family of high performance Output skew: 300ps (maximum), Q0:Q4 and Q/2 clock solutions from IDT. Full 3.3V supply voltage Available in lead-free packages -40C to 85C ambient operating temperature Fully pin and function compatible with the IDTQS5LV931 (including 50, 66 and 80MHz options) Pin Assignment GND 1 20 Q4 2 19 Q/2 OE/nRST FEEDBACK 3 18 GND 4 17 AVDD VDD 5 16 AGND 6 15 7 14 SYNC FREQ SEL 8 13 9 12 GND Q0 10 11 870931I-01 20-Lead QSOP, 150Mil 3.9mm x 8.65mm x 1.5mm package body R Package Top View Block Diagram Q0 2 1 0 Q1 1 0 2 SYNC PLL f f REF VCO 20MHz - 160MHz Q2 Q3 Q4 FEEDBACK 4 Q/2 PLL EN FREQ SEL 2016 Integrated Device Technology, Inc 1 Revision B April 25, 2016870931I-01 Data Sheet Table 1. Pin Descriptions Number Name Type Description 1, 9, 12, 14, 18 GND Power Power supply ground. Output enable and asynchronous reset. Resets all outputs. Logic LOW, the outputs are in 2 OE/nRST Input high-impedance state. Logic HIGH enables all outputs. LVCMOS/LVTTL interface levels. PLL feedback input which is connected to one of the clock outputs to close the PLL 3 FEEDBACK Input feedback loop. LVCMOS/LVTTL interface levels. 4AV Power Positive power supply for the PLL. DD Power 5, 16 V Positive power supply pins. DD 6 AGND Power Power supply ground for the PLL. 7 SYNC Input Single-ended reference clock input. LVCMOS/LVTTL interface levels. Frequency select. Logic LOW level inserts a divide-by-2 into the PLL output and feedback 8 FREQ SEL Input path. Logic HIGH inserts a divide-by-1 into the PLL output and feedback path. LVCMOS/LVTTL interface levels. 10, 11, Q0, Q1, Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 15, 17, 20 Q2, Q3, Q4 PLL enable. Enable and disables the PLL. Logic HIGH enables the PLL. Logic LOW 13 PLL EN Input disables the PLL and the input reference signal is routed to the output dividers (PLL bypass). LVCMOS/LVTTL interface levels. 19 Q/2 Output Single-ended clock output. LVCMOS/LVTTL interface levels. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN C Power Dissipation Capacitance V = AV = 3.6V 330 pF PD DD DD R Output Impedance 11 OUT 2016 Integrated Device Technology, Inc 2 Revision B April 25, 2016