Low Voltage, Low Skew 8732-01 Data Sheet 3.3V LVPECL Clock Generator GENERAL DESCRIPTION Features Ten differential 3.3V LVPECL outputs The 8732-01 is a low voltage, low skew, 3.3V LVPECL Clock Generator. The 8732-01 has two selectable clock inputs. The Selectable differential CLK0, nCLK0 or CLK0, nCLK0 pair can accept most standard differential input LVCMOS/LVTTL CLK1 inputs levels. The single ended clock input accepts LVCMOS or LVTTL CLK0, nCLK0 supports the following input types: input levels. The 8732-01 has a fully integrated PLL along with LVPECL, LVDS, LVHSTL, SSTL, HCSL frequency con gurable outputs. An external feedbackinput and CLK1 accepts the following input levels: outputs regenerate clocks with zero delay. LVCMOS or LVTTL The 8732-01 has multiple divide select pins for each bank of Maximum output frequency: 350MHz outputs along with 3 independent feedback divide select pins VCO range: 250MHz to 700MHz allowing the 8732-01 to function both as a frequency multiplier and divider. The PLL SEL input can be usedto bypass the External feedback for zero delay clock regeneration PLL for test and system debug purposes.In bypass mode, with con gurable frequencies the input clock is routed around the PLLand into the internal Cycle-to-cycle jitter: CLK0, nCLK0, 50ps (maximum) output dividers. CLK1, 80ps (maximum) Output skew: 150ps (maximum) Static phase offset: -150ps to 150ps Lead-Free package fully RoHS compliant BLOCK DIAGRAM PIN ASSIGNMENT 52 51 50 49 48 47 46 45 44 43 42 41 40 V 1 V CCO 39 CCO 2 QA0 38 nQB3 nQA1 5 35 QB2 V EE 6 V 34 EE PLL SEL 7 33 MR ICS8732-01 V V CCO CCO 31 nQA2 10 30 QB1 QA3 11 29 nQB0 nQA3 12 28 QB0 V 13 EE 27 V EE 14 15 16 17 18 19 20 21 22 23 24 25 26 52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View 2016 Integrated Device Technology, Inc 1 Revision E January 22, 2016 DIV SELA1 VEE DIV SELA0 FBDIV SEL2 V FBDIV SEL1 CC FBDIV SEL0 V EE CLK1 nFB IN FB IN nCLK0 VCC CLK0 VEE CLK SEL nQFB0 V CCA QFB0 nc DIV SELB1 nQFB1 QFB1 DIV SELB0 VCC VCCO8732-01 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 8, 32, V Power Output supply pins. CCO 39, 40 2, 3, QA0, nQA0, Output Differential output pair. LVPECL interface levels. 4, 5 QA1, nQA1 6, 13, 17, V Power Negative supply pins. EE 27, 34, 45, 52 Selects between the PLL and reference clock as the input to the dividers. 7 PLL SEL Input Pullup When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS / LVTTL interface levels. 9, 10, 11, QA2, nQA2, Output Differential output pairs. LVPECL interface levels. 12 QA3, nQA3 Determines output divider valued in Table 3. 14 DIV SELA1 Input Pulldown LVCMOS / LVTTL interface levels. Determines output divider valued in Table 3. 15 DIV SELA0 Input Pulldown LVCMOS / LVTTL interface levels. 16, 26, 46 V Power Core supply pins. CC 18 CLK1 Input Pulldown LVCMOS / LVTTL reference clock input. 19 nCLK0 Input Pullup Inverting differential clock input. 20 CLK0 Input Pulldown Non-inverting differential clock input. Clock select input. When LOW, selects CLK0, nCLK0. 21 CLK SEL Input Pulldown When HIGH, selects CLK1. LVCMOS / LVTTL interface levels. 22 V Power Analog supply pin. CCA 23 nc Unused No connect. Determines output divider valued in Table 3. 24 DIV SELB1 Input Pulldown LVCMOS / LVTTL interface levels. Determines output divider valued in Table 3. 25 DIV SELB0 Input Pulldown LVCMOS / LVTTL interface levels. 28, 29, QB0, nQB0, Output Differential output pairs. LVPECL interface levels. 30, 31 QB1, nQB1 Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs 33 MR Input Pulldown nQx to go high. When LOW, the internal dividers and the outputs are en- abled. LVCMOS / LVTTL interface levels. 35, 36, QB2, nQB2, Output Differential output pairs. LVPECL interface levels. 37, 38 QB3, nQB3 41, 42, QFB1, nQFB1, Output Differential feedback output pairs. LVPECL interface levels. 43, 44 QFB0, nQFB0 Feedback input to phase detector for regenerating clocks 47 FB IN Input Pulldown with zero delay. Feedback input to phase detector for regenerating clocks 48 nFB IN Input Pullup with zero delay. Selects divide value for differential feedback output pairs. 49 FBDIV SEL0 Input Pulldown LVCMOS / LVTTL interface levels. Selects divide value for differential feedback output pairs. 50 FBDIV SEL1 Input Pulldown LVCMOS / LVTTL interface levels. Selects divide value for differential feedback output pairs. 51 FBDIV SEL2 Input Pulldown LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 2016 Integrated Device Technology, Inc 2 Revision E January 22, 2016