VDDOB GND PLL SEL FB IN VDDA VDD XTAL SEL FBDIV SEL1 XTAL1 FBDIV SEL0 DIV SELB1 XTAL2 DIV SELB0 REF IN VDDOA DIV SELA1 Low Voltage/Low Skew, 1:8 PCI/PCI-X 87608I Data Sheet Zero Delay clock Generator GENERAL DESCRIPTION FEATURES Fully integrated PLL The 87608I has a selectable REF CLK or crystal input. The REF CLK input accepts LVCMOS or LVTTL input levels. Eight LVCMOS/LVTTL outputs, 15 typical output impedance The 87608I has a fully integrated PLL along with frequency Selectable crystal oscillator interface or con gurable clock and feedback outputs for multiplying and LVCMOS/LVTTL REF IN clock input regenerating clocks with zero delay. Maximum output frequency: 166.67MHz The 87608I is a 1:8 PCI/PCI-X Clock Generator. The 87608I Maximum crystal input frequency: 38MHz has a selectable REF CLK or crystal input. The REF CLK input Maximum REF IN input frequency: 41.67MHz accepts LVCMOS or LVTTL input levels. The 87608I has a fully integrated PLL along with frequency con gurable clock and Individual banks with selectable output dividers for feedback outputs for multiplying and regenerating clocks with generating 33.333MHz, 66.66MHz, 100MHz and 133.333MHz zero delay. The PLLs VCO has an operating range of 250MHz- 500MHz, allowing this device to be used in a variety of general Separate feedback control for generating PCI / PCI-X purpose clocking applications. For PCI/PCI-X applications in frequencies from a 16.66MHz or 20MHz crystal, or 25MHz particular, the VCO frequency should be set to 400MHz. This or 33.33MHz reference frequency can be accomplished by supplying 33.33MHz, 25MHz, 20MHz, VCO range: 200MHz to 500MHz or 16.66MHz on the reference clock or crystal input and by selecting 12, 16, 20, or 24, respectively as the feedback Cycle-to-cycle jitter: 120ps (maximum), 3.3V divide value. The dividers on each of the two output banks can Period jitter, RMS: 20ps (maximum) then be independently con gured to generate 33.33MHz (12), Output skew: 250ps (maximum) 66.66MHz (6), 100MHz (4), or 133.33MHz (3). Bank skew: 60ps (maximum) The 87608I is characterized to operate with its core supply Static phase offset: 160ps 160ps at 3.3V and each bank supply at 3.3V or 2.5V. The 87608I is packaged in a small 7x7mm body LQFP, making it ideal for use Voltage Supply Modes: in space-constrained applications. V (core/inputs), V (analog supply for PLL), DD DDA V (output bank A), DDOA V (output bank B, REF OUT, FB OUT) DDOB V /V /V /V DD DDA DDOA DDOB 3.3/3.3/3.3/3.3 3.3/3.3/2.5/3.3 3.3/3.3/3.3/2.5 3.3/3.3/2.5/2.5 PIN ASSIGNMENT -40C to 85C ambient operating temperature Available in lead-free RoHS compliant package 32 31 30 29 28 27 26 25 QA0 QB0 1 24 QA1 QB1 2 23 ICS87608I GND GND 3 22 32-Lead LQFP QA2 QB2 4 21 7mm x 7mm x 1.4mm QA3 QB3 5 package body 20 VDDOA VDDOB 6 19 Y package MR Top View REF OUT 7 18 DIV SELA0 FB OUT 8 17 9 10 11 12 13 14 15 16 2016 Integrated Device Technology, Inc 1 Revision C January 25, 201687608I Data Sheet BLOCK DIAGRAM 2016 Integrated Device Technology, Inc 2 Revision C January 25, 2016