Low Skew, 1-to-15, 87974I Data Sheet LVCMOS/LVTTL Clock Generator GENERAL DESCRIPTION FEATURES The 87974I is a low skew, low jitter 1-to-15 LVCMOS/ Fully integrated PLL LVTTL Clock Generator/Zero Delay Buffer. The device Fifteen single ended 3.3V LVCMOS/LVTTL outputs has a fully integrated PLL and three banks whose divider Two LVCMOS/LVTTL clock inputs for redundant clock applica- ratios can be independently controlled, providing output tions frequency relationships of 1:1, 2:1, 3:1, 3:2, 3:2:1. In addition, the external feedback connection provides for a wide CLK0 and CLK1 accepts the following input levels: selection of output-to-input frequency ratios. The CLK0 and LVCMOS/LVTTL CLK1 pins allow for redundant clocking on the input and dynam- Output frequency range: 8.33MHz to 125MHz ically switching the PLL between two clock sources. VCO range: 200MHz to 500MHz Guaranteed low jitter and output skew characteristics make External feedback for zero delay clock regeneration the 87974I ideal for those applications demanding well de ned performance and repeatability. Cycle-to-cycle jitter: 100ps (typical) Output skew: 350ps (maximum) 3.3V operating supply -40C to 85C ambient operating temperature Available in lead-free RoHS-compliant package PIN ASSIGNMENT 52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View 2016 Integrated Device Technology, Inc 1 Revision E January 26, 201687974I Data Sheet BLOCK DIAGRAM 2016 Integrated Device Technology, Inc 2 Revision E January 26, 2016