8SLVD1212 Datasheet 1:12, LVDS Output Fanout Description Features Twelve low skew, low additive jitter LVDS output pairs The 8SLVD1212 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, Two selectable, differential clock input pairs very low additive phase-noise clock and data signals. Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL, CML The 8SLVD1212 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew Maximum input clock frequency: 2GHz (maximum) characteristics make the device ideal for clock distribution LVCMOS/LVTTL interface levels for the control input select applications that demand well-defined performance and pins repeatability. Output skew: 40ps (maximum) Two selectable differential inputs and twelve low skew outputs are Propagation delay: 310ps (typical) available. The integrated bias voltage reference enables easy Low additive phase jitter, RMS f = 156.25MHz, REF interfacing of single-ended signals to the device inputs. 10kHz to 20MHz: 77fs (typical) The 8SLVD1212 is optimized for low power consumption and low Device current consumption (I ): 213mA (maximum) DD additive phase noise. 2.5V supply voltage Lead-free (RoHS 6), 6 6 mm, 40-VFQFN packaging -40C to 85C ambient operating temperature Block Diagram 8SLVD1212 Q0 nQ0 Voltage V REF0 Reference Q1 nQ1 VDD Q2 nQ2 PCLK0 Q3 nPCLK0 nQ3 GND Q4 nQ4 fREF V DD Q5 nQ5 PCLK1 Q6 nPCLK1 nQ6 Q7 GND nQ7 VDD Q8 SEL nQ8 Q9 GND nQ9 Q10 nQ10 Voltage V REF1 Reference Q11 nQ11 2021 Renesas Electronics Corporation 1 February 2, 20218SLVD1212 Datasheet Contents Description 1 Features 1 Pin Assignments 3 Pin Descriptions and Characteristics 3 Function Table 5 Absolute Maximum Ratings . 5 DC Electrical Characteristics 6 AC Electrical Characteristics 7 Additive Phase Jitter . 8 Parameter Measurement Information 9 Applications Information . 11 Recommendations for Unused Input and Output Pins . 11 Inputs 11 Outputs . 11 Wiring the Differential Input to Accept Single-Ended Levels . 11 2.5V LVPECL Clock Input Interface . 12 LVDS Driver Termination . 13 VFQFN EPAD Thermal Release Path . 13 Power Considerations (8SLVD1212A) 14 Reliability Information . 15 Transistor Count 15 Package Outline Drawings . 15 Marking Diagram 15 Ordering Information . 16 Revision History . 17 2021 Renesas Electronics Corporation 2 February 2, 2021