FemtoClock NG IDT8T49N105I Universal Frequency Translator DATA SHEET General Description Features The IDT8T49N105I is a highly flexible FemtoClock NG general Fourth generation FemtoClock NG technology purpose, low phase noise Universal Frequency Translator / Universal Frequency Translator (UFT) / Frequency Synthesizer Synthesizer with alarm and monitoring functions suitable for Single output (Q, nQ), programmable as LVPECL or LVDS networking and communications applications. It is able to generate Zero ppm frequency translation any output frequency in the 0.98MHz - 312.5MHz range and most output frequencies in the 312.5MHz - 1,300MHz range (see Table 3 Single differential input supports the following input types: LVPECL, LVDS, LVHSTL, HCSL for details). A wide range of input reference clocks and a range of low-cost fundamental mode crystal frequencies may be used as the Input frequency range: 8kHz - 710MHz source for the output frequency. Crystal input frequency range: 16MHz - 40MHz The IDT8T49N105I has three operating modes to support a very Two factory-set register configurations for power-up default state broad spectrum of applications: Power-up default configuration pin or register selectable 1) Frequency Synthesizer Configurations customized via One-Time Programmable ROM Synthesizes output frequencies from a 16MHz - 40MHz 2 Settings may be overwritten after power-up via I C fundamental mode crystal. 2 I C Serial interface for register programming Fractional feedback division is used, so there are no requirements for any specific crystal frequency to produce the RMS phase jitter at 155.52MHz, using a 40MHz crystal LVDS desired output frequency with a high degree of accuracy. Output (12kHz - 20MHz): 439fs (typical), Low Bandwidth Mode (FracN) 2) High-Bandwidth Frequency Translator RMS phase jitter at 400MHz, using a 40MHz crystal Applications: PCI Express, Computing, General Purpose (12kHz - 40MHz):285fs (typical), Synthesizer Mode (Integer FB) Translates any input clock in the 16MHz - 710MHz frequency Output supply voltage modes: range into any supported output frequency. V /V /V CC CCA CCO This mode has a high PLL loop bandwidth in order to track input 3.3V/3.3V/3.3V reference changes, such as Spread-Spectrum Clock 3.3V/3.3V/2.5V (LVPECL only) modulation, so it will not attenuate much jitter on the input reference. 2.5V/2.5V/2.5V 3) Low-Bandwidth Frequency Translator -40C to 85C ambient operating temperature Applications: Networking & Communications. Lead-free (RoHS 6) packaging Translates any input clock in the 8kHz -710MHz frequency range into any supported output frequency. Pin Assignment This mode supports PLL loop bandwidths in the 10Hz - 580Hz range and makes use of an external crystal to provide significant jitter attenuation. This device provides two factory-programmed default power-up configurations burned into One-Time Programmable (OTP) memory. The configuration to be used is selected by the CONFIG pin. The two 3029 28 27 26 25 24 23 22 21 configurations are specified by the customer and are programmed by nc 31 20 nc nc 32 19 nc IDT during the final test phase from an on-hand stock of blank 8T49N105 LF0 33 18 S A0 devices. The two configurations may be completely independent of 40 Lead VFQFN one another. LF1 34 17 S A1 V 35 6mm x 6mm x 0.925mm 16 CONFIG EE One usage example might be to install the device on a line card with V 36 15 SCLK E-Pad 4.65mm x 4.65mm CCA two optional daughter cards: an OC-12 option requiring a 622.08MHz HOLDOVER 37 14 SDATA K Package LVDS clock translated from a 19.44MHz input and a Gigabit Ethernet CLKBAD 38 13 V CC Top View option requiring a 125MHz LVPECL clock translated from the same nc 39 12 PLL BYPASS 19.44MHz input reference. XTALBAD 40 11 nc 12 3 45 67 89 10 To implement other configurations, these power-up default settings 2 can be overwritten after power-up using the I C interface and the device can be completely reconfigured. However, these settings would have to be re-written next time the device powers-up. IDT8T49N105ANLGI REVISION A MAY 24, 2013 1 2013 Integrated Device Technology, Inc. XTAL IN LOCK IND XTAL OUT V CC V OE CC nc Q CLK nQ nCLK V CCO V nc CC V nc EE nc nc nc V EE IDT8T49N105I Data Sheet FemtoClock NG Universal Frequency Translator Complete Block Diagram IDT8T49N105ANLGI REVISION A MAY 24, 2013 2 2013 Integrated Device Technology, Inc.