FemtoClock NG Octal Universal 8T49N282 Frequency Translator Datasheet Description Features The 8T49N282 has two independent, fractional-feedback PLLs that Supports SDH/SONET and Synchronous Ethernet clocks including all FEC rate conversions can be used as jitter attenuators and frequency translators. It is equipped with six integer and two fractional output dividers, allowing Two differential outputs meet jitter limits for 100G Ethernet and the generation of up to eight different output frequencies, ranging STM-256/OC-768 from 8kHz to 1GHz. Four of these frequencies are completely <0.3ps RMS (including spurs): 12kHz to 20MHz independent of each other and the inputs. The other four are related All outputs <0.5ps RMS (including spurs) 12kHz to 20MHz frequencies. The eight outputs may select among LVPECL, LVDS or Operating modes: locked to input signal, holdover and free-run LVCMOS output levels. Initial holdover accuracy of 50ppb This functionality makes it ideal to be used in any frequency Accepts up to four LVPECL, LVDS, LVHSTL, HCSL or LVCMOS translation application, including 1G, 10G, 40G and 100G input clocks Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T Accepts frequencies ranging from 8kHz up to 875MHz G.709 (2009) FEC rates. The device may also behave as a frequency Auto and manual input clock selection with hitless switching synthesizer. Clock input monitoring, including support for gapped clocks The 8T49N282 accepts up to four differential or single-ended input clocks and a crystal input. Each of the two internal PLLs can lock to Phase-Slope Limiting and Fully Hitless Switching options to control output phase transients different input clocks which may be of independent frequencies. The other two input clocks are intended for redundant backup of the Operates from a 10MHz to 40MHz fundamental-mode crystal primary clocks and must be related in frequency to their primary. Generates eight LVPECL / LVDS or 16 LVCMOS output clocks The device supports hitless reference switching between input Output frequencies ranging from 8kHz up to 1.0GHz (diff) clocks. The device monitors all input clocks for Loss of Signal (LOS), Output frequencies ranging from 8kHz to 250MHz (LVCMOS) and generates an alarm when an input clock failure is detected. Eight General Purpose I/O pins with optional support for status Automatic and manual hitless reference switching options are and control supported. LOS behavior can be set to support gapped or un-gapped Eight Output Enable control inputs clocks. Lock, Holdover and Loss-of-Signal status outputs The 8T49N282 supports holdover for each PLL. The holdover has an Open-drain Interrupt pin initial accuracy of 50ppB from the point where the loss of all Write-protect pin to prevent configuration registers being altered applicable input reference(s) has been detected. It maintains a historical average operating point for each PLL that may be returned Programmable PLL bandwidth settings for each PLL: to in holdover at a limited phase slope. 0.5Hz, 1Hz, 2Hz, 4Hz, 8Hz, 16Hz, 32Hz, 64Hz, 128Hz, 256Hz or 512Hz The device places no constraints on input to output frequency conversion, supporting all FEC rates, including the new revision of Optional Fast Lock function ITU-T Recommendation G.709 (2009), most with 0ppm conversion Programmable output phase delays in steps as small as 16ps error. 2 2 Register programmable through I C / SPI or via external I C Each PLL has a register-selectable loop bandwidth from 0.5Hz to EEPROM 512Hz. Bypass clock paths for system tests Each output supports individual phase delay settings to allow Power supply modes: output-output alignment. V / V / V CC CCA CCO 3.3V / 3.3V / 3.3V The device supports Output Enable inputs and Lock, Holdover and 3.3V / 3.3V / 2.5V LOS status outputs. 3.3V / 3.3V / 1.8V (LVCMOS) 2 The device is programmable through an I C interface. It also supports 2.5V / 2.5V / 3.3V 2 I C master capability to allow the register configuration to be read 2.5V / 2.5V / 2.5V from an external EEPROM. The user may select whether the 2.5V / 2.5V / 1.8V (LVCMOS) 2 programming interface uses I C protocols or SPI protocols, however Power down modes support consumption as low as 1.7W (see in SPI mode, read from the external EEPROM is not supported. Power Dissipation and Thermal Considerations section for details) Typical Applications -40C to 85C ambient operating temperature Package: 72QFN, lead-free RoHs (6) OTN or SONET / SDH equipment Line cards (up to OC-192, and supporting FEC ratios) OTN de-mapping (Gapped Clock and DCO mode) Gigabit and Terabit IP switches / routers including support of Synchronous Ethernet Wireless base station baseband Data communications 2019 Integrated Device Technology, Inc. 1 January 28, 20198T49N282 Datasheet 8T49N282 Block Diagram IntN Output Q0 Divider Fractional Feedback XTAL APLL 0 IntN Output OSC Q1 Divider Lock 0 Input Clock Holdover 0 Monitoring, FracN Output Clk0 P0 Priority, Q2 Fractional Divider & Clk1 P1 Feedback Selection APLL 1 FracN Output Clk2 P2 Q3 Divider Lock 1 Clk3 P3 Holdover 1 IntN Q4 Reset nRST IntN Q5 LOS Logic Status Registers GPIO Logic OTP 2 IntN Q6 I C Master Control Registers SCLK 8 2 I C Slave SDATA Q7 IntN Serial EEPROM nINT PLL BYP GPIO nWP SA0, SA1 Figure 1. 8T49N282 Functional Block Diagram 2019 Integrated Device Technology, Inc. 2 January 28, 2019