Programmable FemtoClock NG LVPECL/LVDS IDT8T49N524I Dual 4-Output Fractional Clock Generator DATA SHEET General Description Features The IDT8T49N524I is an eight output programmable any-rate dual Fourth Generation FemtoClock NG PLL technology clock generator with selectable LVDS or LVPECL outputs. Both clock Eight outputs selectable as LVPECL or LVDS generators use Fractional Output Dividers to be able to generate out- Input selectable: fundamental mode crystal or clock reference put frequencies that are independent of each other and independent Supports fundamental mode crystals from 10MHz - 40MHz of the input frequency. Output frequencies for both clock generators are generated from a single crystal or reference clock. CLK, nCLK input pair can accept the following differential input levels: LVPECL, LVDS, HCSL Clock Generator A supports three different factory-programmed Input frequencies from 5MHz up to 800MHz default frequencies that can be selected from using only the FSEL control pins. Alternatively any desired output frequency can be Two independent output frequencies can be generated 2 programmed over the I C serial port. The chosen output frequency is Output frequencies independent of each other and of input then driven out the QA0 to QA3 outputs. Output frequencies from 15.234MHz - 645MHz, and Clock Generator B supports a single factory-programmed default 975MHz - 1290MHz, (See Table 5D for details) frequency. It can also be programmed for any output frequency via RMS phase jitter at 125MHz (12kHz - 20MHz): 0.282ps (typical) the serial port. The output frequency is driven out the QB0 to QB3 RMS phase jitter at 156.25MHz (12kHz - 20MHz): outputs. 0.278ps (typical) Some examples of frequency configurations that can be achieved Full 2.5V or 3.3V power supply are shown in Table 5A. Please consult IDT for programming software 2 I C programming interface that can be used to determine the required settings for any desired -40C to 85C ambient operating temperature configuration. Lead-free (RoHS 6) packaging Excellent phase noise performance is achieved with IDTs fourth NG PLL technology, which delivers Generation FemtoClock V / V / V CC CCA CCO sub-0.5ps RMS phase jitter in the integer divide mode. 3.3V / 3.3V / 3.3V 3.3V / 3.3V / 2.5V (LVPECL only) 2.5V / 2.5V / 2.5V Pin Assignment 3029 28 27 26 25 24 23 22 21 VEE B 31 20 FSEL1 SCLK 32 19 V CC IDT8T49N524I SDATA 33 V 18 EE VEE 34 40 Lead VFQFN ADDR SEL 17 V 35 6mm x 6mm x 0.925mm 16 FSEL0 CCA 4.65mm x 4.65mm EPad 15 LOCK 36 nCLK 37 NL Package CLK V 14 EE V 38 CC 13 VEE Top View 39 12 CLK SEL XTAL OUT 40 VEE A 11 XTAL IN 12 3 45 6 7 89 10 IDT8T49N524NLGI REVISION A JANUARY 23, 2014 1 2014 Integrated Device Technology, Inc. QA0 QB0 nQA0 nQB0 QA1 QB1 nQA1 nQB1 VCCO B V CCO A QB2 QA2 nQB2 nQA2 QB3 QA3 nQB3 nQA3 VEE A VEE B IDT8T49N524I Data Sheet PROGRAMMABLE FEMTOCLOCK NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR Block Diagram LOCK QA0 nQA0 Pulldown NINT 1 5:0 CLK SEL QA1 2 0 NFRAC 1 15:0 nQA1 QA2 XTAL IN 1 2 Xtal nQA2 0 1 Osc XTAL OUT QA3 Phase x2 Detector Pulldown nQA3 FemtoClock NG CLK 1 P 1:0 + 0 PU/PD VCO nCLK Charge QB0 Pump nQB0 2 1 QB1 NINT 2 5:0 nQB1 0 MINT 8:1 2 QB2 NFRAC 2 15:0 nQB2 Pulldown FSEL0 Divider, QB3 Pulldown FSEL1 Output Type nQB3 Pullup & OUTPUT ENABLE 8 SCLK Output OUTPUT STYLE Pullup SDATA Enable Pulldown ADDR SEL Selection IDT8T49N524NLGI REVISION A JANUARY 23, 2014 2 2014 Integrated Device Technology, Inc.