Datasheet 8V19N882 RF Sampling Clock Generator and Jitter Attenuator The 8V19N882 is a fully integrated FemtoClock RF Features Sampling Clock Generator and Jitter Attenuator. The High-performance clock RF sampling clock device is designed as a high-performance clock generator and clock jitter attenuator with support solution for conditioning and frequency/phase for JESD204B/C management of wireless base station radio Low phase noise: -144.7dBc/Hz (800kHz offset equipment boards. The 8V19N882 is optimized to 491.52MHz) deliver excellent phase noise performance as Integrated phase noise of 74fs RMS (12k-20MHz, required in 4G, 5G, and including mmWave radio 491.52MHz) implementations. The device supports JESD204B (subclass 0 and 1) and JESD204C. Dual-PLL architecture with internal and optional external VCO A two-stage PLL architecture supports both jitter Eight output channels with a total of 16 outputs attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external Configurable integer clock frequency dividers VCXO for best possible phase noise characteristics. Clock output frequencies: up to 3932.16MHz The second stage PLL locks on the first PLL output (Internal VCO) and 6GHz (optional external VCO) signal and synthesizes the target frequency. The Differential, low noise I/O second stage PLL can use the internal or an external Deterministic phase delay and integrated phase high-frequency VCO. delay circuits The 8V19N882 generates the high-frequency clocks Redundant input clock architecture with two inputs and the low-frequency synchronization signals and monitors, holdover, and input switching (SYSREF) from the selected VCO. SYSREF signals SPI 3/4 wire configuration interface are internally synchronized to the clock signals. The Supply voltage: 1.8V, 2.5V, and 3.3V integrated signal delay blocks can be used to achieve phase alignment, controlled phase offsets between Package: 76 VFQFN (9 x 9 mm) system reference and clock signals, and to Temperature range: -40C to +105C (board) align/delay individual output signals. The two redundant inputs are monitored for activity. Four Applicable Standards selectable clock switching modes can handle clock JESD204B and C input failure scenarios. Auto-lock, individually programmable output frequency dividers, and phase Applications adjustment capabilities are added for flexibility. Wireless infrastructure applications: 4G, 5G, and The 8V19N882 is configured through a 3/4-wire SPI mmWave interface and reports lock and signal loss status in Data acquisition: jitter-sensitive ADC and DAC internal registers and via the GPIO 1:0 outputs. circuits Internal status bit changes can also be reported via a Radar, imaging, instrumentation, and medical GPIO output. VCXO LO clock output (8V97003) Input Switch 2 Monitor PLL-0 (VCXO) PLL-1 Clocks Holdover 2 18 Differential 8 Output Channels Clock /SYSREF Frequency Dividers SYSREF Generator Outputs SYSREF Phase Delay Synchronziation 16 (DAC, ADC) Figure 1. Simplified Block Diagram X0116802 Rev.1.1 Page 1 Mar.11.21 2021 Renesas Electronics8V19N882 Datasheet Contents 1. Block Diagram . 4 2. Features (Full List) . 5 3. Pin Information 6 3.1 Pin Assignments . 6 3.2 Pin Descriptions . 7 4. Principles Of Operation 10 4.1 Overview 10 4.2 Phase-Locked Loop Operation . 10 4.2.1 Frequency Generation 10 4.2.2 PLL Description 14 4.2.3 PLL-0 (VCXO-PLL) Lock Detect . 16 4.2.4 PLL-1 Lock Detect . 17 4.3 Output Channel and JESD204B/C Logic . 17 4.3.1 Channel Description 17 4.3.2 Clock Delay Circuits 19 4.3.3 Differential Outputs . 21 4.4 Redundant Clock Inputs 23 4.4.1 Monitoring and LOS of Input Signal 23 4.4.2 Input Re-Validation . 23 4.4.3 Clock Selection 24 4.4.4 Holdover . 24 4.4.5 Input Priorities . 24 4.4.6 Hold-off Counter . 24 4.5 Revertive Switching 25 4.6 Configuration for JESD204B Operation 25 4.6.1 SYSREF Generation 25 4.6.2 Clock to SYSREF Phase Alignment 28 4.7 General Purpose Input/Outputs (GPIO 1:0 ) 30 4.7.1 GPIO Pin Configuration . 30 4.7.2 GPIO Pin Configuration at Startup . 31 4.8 Status Conditions and Interrupts 31 4.9 Power-Down Features 33 4.10 Device Startup, Reset, and Synchronization . 33 4.10.1 Recommended Configuration Sequence (In Order) 33 4.10.2 Changing Frequency Dividers and Phase Delay Values . 34 4.11 SPI Interface . 35 5. Register Descriptions 39 5.1 Register Map . 39 5.2 Register Descriptions 41 5.2.1 Device Configuration Registers . 41 5.2.2 Input, PLL-0 Frequency Divider and Control Registers . 43 5.2.3 PLL-0 Charge Pump Control Registers . 45 5.2.4 PLL-1 Input and Bypass Control Registers . 46 5.2.5 PLL-1 Charge Pump Control Registers . 47 5.2.6 PLL-1 Feedback Control Registers . 48 5.2.7 Reference Switching Registers 49 X0116802 Rev.1.1 Page 2 Mar.11.21