952926 Datasheet Programmable Timing Control Hub for Next Gen P4 processor Recommended Application: Key Specifications: VIA VX/CX 700 style chipset for P4 processor CPU-CPU +/-250ps CPU/SRC outputs cycle-cycle jitter < 125ps Output Features: 3V66 outputs cycle-cycle jitter < 250ps 3 - 0.7V current-mode differential CPU pairs PCI outputs cycle-cycle jitter < 250ps 10 - PCI, 3 free running, 33MHz AGP leads CPU between .75 to -3ns 2 - REF, 14.318MHz CPU-PCI skew between 1.6 to -1.5ns 3 - 3V66, 66.66MHz 1 - 48MHz Features/Benefits: 1 - 24/48MHz Programmable output frequency. 2 - 25MHz, 2 free running 2.5V or 3.3V Programmable asynchronous 3V66&PCI frequency. Programmable output divider ratios. Programmable output skew. Functionality Programmable spread percentage for EMI control. Bit4 Bit3 Bit2 Bit1 Bit0 CPU AGP PCI Watchdog timer technology to reset system if system FS4 FS3 FS2 FS1 FS0 MHz MHz MHz malfunctions. 100.00 66.67 33.33 0 0 000 Programmable watch dog safe frequency. 200.00 66.67 33.33 0 0 001 Support I2C Index read/write and block read/write 133.33 66.67 33.33 0 0 010 operations. 166.67 66.67 33.33 0 0 011 Uses external 14.318MHz reference input. 0 0 1 0 0 200.00 66.67 33.33 400.00 66.67 33.33 0 0 101 Pin Configuration 0 0 110 266.67 66.67 33.33 333.33 66.67 33.33 0 0 111 *FS1/REF0 1 48 VDDA 100.99 67.33 33.66 0 1 000 **FS0/REF1 2 47 GND 201.98 67.33 33.66 VDDREF 3 46 IREF 0 1 001 X1 4 45 CPUCLKT ITP/(PCI STOP ) 0 1 010 134.65 67.33 33.66 X2 5 44 CPUCLKC ITP/(CPU STOP ) 0 1 011 168.31 67.32 33.66 GND 6 43 GND **FS2/PCICLK F0 7 42 CPUCLKT1 01 1 00 115.00 76.67 38.33 **FS4/PCICLK F1 8 41 CPUCLKC1 0 1 101 230.00 76.67 38.33 PCICLK F2 9 40 VDDCPU 0 1 110 153.33 76.66 38.33 VDDPCI 10 39 CPUCLKT0 11 38 CPUCLKC0 GND 191.67 76.67 38.33 0 1 111 12 37 **MODE/PCICLK0 GND 1 100.00 66.66 33.33 0 000 PCICLK1 13 36 25Mhz 0F 200.00 66.66 33.33 PCICLK2 14 35 25Mhz 1F 1 0 001 15 34 PCICLK3 VDD25M 133.33 66.66 33.33 1 0 010 16 33 VttPWR GD/PD /WOL STOP PCICLK4 166.67 71.43 35.71 1 0 011 17 32 SDATA VDDPCI 18 31 SCLK 0 1 0 0 200.00 66.66 33.33 GND 1 PCICLK5 19 30 Reset 400.00 66.66 33.33 1 0 101 20 29 PCICLK6 3V66 0 1 0 110 266.67 66.66 33.33 **FS3/48MHz 21 28 GND **Sel24 48 /24 48MHz 22 27 VDD3V66 1 0 111 333.33 66.66 33.33 23 26 GND 3V66 1 1 1 000 105.00 69.99 35.00 24 25 3V66 2 VDD48 1 1 001 210.00 69.99 35.00 * This pin have 120K pull-up to VDD 1 1 010 140.00 69.99 35.00 ** This pin have 120K pull-down to GND 175.00 69.99 35.00 1 1 011 1 110.00 73.33 36.66 11 00 48-pin SSOP & TSSOP 220.00 73.33 36.66 1 1 101 1 1 110 146.66 73.33 36.66 1 1 111 183.34 73.33 36.66 125403/16/07 ICS952926 952926 Datasheet Pin Description Pin PIN NAME PIN TYPE DESCRIPTION 1 *FS1/REF0 I/O Frequency select latch input pin / 14.318 MHz reference clock. 2 **FS0/REF1 I/O Frequency select latch input pin / 14.318 MHz reference clock. 3 VDDREF PWR Ref, XTAL power supply, nominal 3.3V 4 X1 IN Crystal input, Nominally 14.318MHz. 5 X2 OUT Crystal output, Nominally 14.318MHz 6 GND PWR Ground pin. 7 **FS2/PCICLK F0 I/O Frequency select latch input pin / 3.3V PCI free running clock output. 8 **FS4/PCICLK F1 I/O Frequency select latch input pin / 3.3V PCI free running clock output. 9 PCICLK F2 OUT Free running PCI clock not affected by PCI STOP . 10 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 11 GND PWR Ground pin. Function select latch input pin, 0=Desktop Mode (pin 44/45 are outputs), 1=Mobile Mode (pin44/45 are STOP 12 **MODE/PCICLK0 I/O inputs) / PCI clock output. 13 PCICLK1 OUT PCI clock output. 14 PCICLK2 OUT PCI clock output. 15 PCICLK3 OUT PCI clock output. 16 PCICLK4 OUT PCI clock output. 17 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 18 GND PWR Ground pin. 19 PCICLK5 OUT PCI clock output. 20 PCICLK6 OUT PCI clock output. 21 **FS3/48MHz I/O Frequency select latch input pin / Fixed 48MHz clock output. 3.3V 22 **Sel24 48 /24 48MHz I/O Latched select input for 24/48MHz output / 24/48MHz clock output. 1=24MHz, 0 = 48MHz. 23 GND PWR Ground pin. 24 VDD48 PWR Power pin for the 48MHz output.3.3V 25 3V66 2 OUT 3.3V 66.66MHz clock output 26 3V66 1 OUT 3.3V 66.66MHz clock output 27 VDD3V66 PWR Power pin for the 3.3V 66MHz clocks. 28 GND PWR Ground pin. 29 3V66 0 OUT 3.3V 66.66MHz clock output Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is active 30 Reset OUT low. 31 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 32 SDATA I/O Data pin for SMBus circuitry, 5V tolerant. Active high 3.3V LVTTL input, level sensitive strobe used to determine when latch inputs are valid to sample 33 VttPWR GD/PD /WOL STOP IN /Asynchronous active low input pin used to power down the device into a low power state. / Asynchronous active low input pin that stops all outputs except free running 25Mhz. 34 VDD25M PWR Power supply, nominal 2.5V or 3.3V 35 25Mhz 1F OUT Free running 25MHz clock output, 2.5V or 3.3V (not affected by WOL STOP ). Default set to stoppable. Default free running 25MHz clock output, 2.5V or 3.3V (not affected by WOL STOP ). Default set to Free- 36 25Mhz 0F OUT g. runnin 37 GND PWR Ground pin. Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are 38 CPUCLKC0 OUT required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required 39 CPUCLKT0 OUT for voltage bias. 40 VDDCPU PWR Supply for CPU clocks, 3.3V nominal Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are 41 CPUCLKC1 OUT required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required 42 CPUCLKT1 OUT for voltage bias. 43 GND PWR Ground pin. Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are 44 CPUCLKC ITP/(CPU STOP ) I/O required for voltage bias. / Stops all CPUCLK besides the free running clocks True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required 45 CPUCLKT ITP/(PCI STOP ) I/O for voltage bias. / Stops all PCICLK besides the free running clocks This pin establishes the reference current for the differential current-mode output pairs. This pin requires a 46 IREF OUT fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 47 GND PWR Ground pin. 48 VDDA PWR 3.3V power for the PLL core. 125403/16/07 2