2 O/P 1.5V PCIe Gen1-2-3 Clock Generator 9FGU0241 w/Zo=100ohms DATASHEET Description Features/Benefits The 9FGU0241 is a member of IDT s 1.5V Ultra-Low-Power Direct connection to 100ohm transmission lines saves 16 PCIe clock family with integrated output terminations resistors compared to standard PCIe devices providing Zo=100. The device has 2 output enables for 23mW typical power consumption reduced thermal clock management, 2 different spread spectrum levels in concerns addition to spread off and 2 selectable SMBus addresses. OE pins support DIF power management Programmable Slew rate for each output allows tuning for Recommended Application various line lengths Programmable output amplitude allows tuning for various 1.5V PCIe Gen1-2-3 clock generator application environments DIF outputs blocked until PLL is locked clean system Output Features start-up 2 - 100MHz Low-Power (LP) HCSL DIF pairs w/Zo=100 Selectable 0%, -0.25% or -0.5% spread on DIF outputs 1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL) reduces EMI support External 25MHz crystal supports tight ppm with 0 ppm synthesis error Key Specifications Configuration can be accomplished with strapping pins SMBus interface not required for device control DIF cycle-to-cycle jitter <50ps Selectable SMBus addresses multiple devices can easily DIF output-to-output skew <50ps share an SMBus segment DIF phase jitter is PCIe Gen1-2-3 compliant 3.3V tolerant SMBus interface works with legacy controllers REF phase jitter is < 3.0ps RMS Space saving 24-pin 4x4 mm VFQFPN minimal board space Block Diagram XIN/CLKIN 25 REF1.5 OSC X2 vOE(1:0) DIF1 SS Capable PLL DIF0 vSADR vSS EN tri CKPWRGD PD CONTROL SDATA 3.3 LOGIC SCLK 3.3 9FGU0241 OCTOBER 18, 2016 1 2016 Integrated Device Technology, Inc.9FGU0241 DATASHEET Pin Configuration 24 23 22 21 20 19 XIN/CLKIN 25 1 DIF1 18 X2 2 17 DIF1 VDDXTAL1.5 3 VDDA1.5 16 9FGU0241 vSADR/REF1.5 4 15 GNDA GNDREF 5 DIF0 14 GNDDIG 613DIF0 7 8 9 10 11 12 24-pin VFQFPN, 4x4 mm, 0.5mm pitch prefix indicates internal 120KOhm pull up resistor v prefix indicates internal 120KOhm pull down resistor SMBus Address Selection Table SADR Address + Read/Write Bit State of SADR on first application 0 1101000 x of CKPWRGD PD 1 1101010 x Power Management Table SMBus DIFx CKPWRGD PD REF OE bit True O/P Comp. O/P 1 0 X Low Low Hi-Z 1 1 Running Running Running 1 0 Low Low Low 1. REF is Hi-Z until the 1st assertion of CKPWRGD PD high. After this, when CKPWRG PD is low, REF is Low. Power Connections Pin Number Description VDD GND 35,24 XTAL, REF 76 Digital Power 11,20 10,21 DIF outputs 16 15 PLL Analog 2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS 2 OCTOBER 18, 2016 VDDDIG1.5 GNDXTAL SCLK 3.3 vSS EN tri SDATA 3.3 CKPWRGD PD GND GND VDD1.5 VDD1.5 vOE0 vOE1