REF1.8 DATASHEET 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 9FGV0231 Description Features/Benefits The 9FGV0231 is a 2-output very low-power clock 1.8V operation reduced power consumption generator for PCIe Gen 1, 2, 3 and 4 Common Clocked OE pins support DIF power management (CC) applications. The device has 2 output enables for LP-HCSL differential clock outputs reduced power and clock management and supports 2 different spread board space spectrum levels in addition to spread off. Programmable Slew rate for each output allows tuning for various line lengths Recommended Application Programmable output amplitude allows tuning for PCIe Gen1-4 clock generation for Riser Cards, Storage, various application environments Networking, JBOD, Communications, Access Points DIF outputs blocked until PLL is locked clean system Output Features start-up Selectable 0%, -0.25% or -0.5% spread on DIF outputs 2 - 0.7V low-power HCSL-compatible (LP-HCSL) DIF reduces EMI pairs External 25MHz crystal supports tight ppm with 0 ppm 1 - 1.8V LVCMOS REF output w/Wake-On-LAN (WOL) synthesis error support Configuration can be accomplished with strapping pins Key Specifications SMBus interface not required for device control 3.3V tolerant SMBus interface works with legacy DIF cycle-to-cycle jitter <50ps controllers DIF output-to-output skew <50ps Space saving 4 x 4 mm 24-VFQFPN minimal board PCIe Gen1-2-3-4 CC-compliant space REF phase jitter is < 1.5ps RMS Block Diagram X1 25 OSC X2 OE(1:0) 2 SS Capable PLL DIF(1:0) SADR SS EN tri CONTROL CKPWRGD PD LOGIC SDATA 3.3 SCLK 3.3 IDT 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 1 9FGV0231 JUNE 6, 20199FGV0231 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Pin Configuration 24 23 22 21 20 19 X1 25 1 DIF1 18 X2 2 DIF1 17 VDDXTAL1.8 3 VDDA1.8 16 9FGV0231 vSADR/REF1.8 4 GNDA 15 GNDREF 5 DIF0 14 GNDDIG 613DIF0 7 8 9 10 11 12 24-pin VFQFPN, 4x4 mm, 0.5mm pitch prefix indicates internal 120KOhm pull up resistor v prefix indicates internal 120KOhm pull down resistor SMBus Address Selection Table + Read/Write Bit SADR Address x State of SADR on first application 0 1101000 x of CKPWRGD PD 1 1101010 Power Management Table SMBus DIFx CKPWRGD PD REF OE bit True O/P Comp. O/P 1 0 X Low Low Hi-Z 1 1 Running Running Running 1 0 Low Low Low 1. REF is Hi-Z until the 1st assertion of CKPWRGD PD high. After this, when CKPWRG PD is low, REF is Low. Power Connections Pin Number Description VDD GND 35,24 XTAL, REF 76 Digital 11,20 10,21 DIF outputs 16 15 PLL Analog IDT 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 2 9FGV0231 JUNE 6, 2019 VDDDIG1.8 GNDXTAL SCLK 3.3 vSS EN tri SDATA 3.3 CKPWRGD PD GND GND VDD1.8 VDD1.8 vOE0 vOE1