Datasheet R19DS0069EJ0107 Rev.1.07 TPS-1 th Jul 30 , 2018 Single Chip Interface Solution for PROFINET IO Devices DESCRIPTION The TPS-1 is a single-chip PROFINET interface component integrating a CPU, a 2-port switch supporting latest PROFINET specifications, the Ethernet PHYs and peripheral modules to interface to the application layer of any application building a PROFINET IO device. The internal structure is designed to fulfill the requirements of the IRT protocol. The integrated components realize the complete interface functionality. TPS-1 rounds off the basic technology range of PROFINET specifically for compact devices, and complies with PROFINET specification 2.3. Detailed functions are described in the following users manual. Be sure to read this manual when you design your systems. TPS-1 Users Manual: Hardware (R19UH0081ED) FEATURES Applications Industrial Drives Compact and modular Remote I/Os Product features Integrated PROFINET IO CPU Compliant with Conformance Class C 2 Ethernet ports, 100 Mbps, full duplex 2 integrated PHYs with an auto negotiation, auto crossover Integrated IRT switch, 8 priority levels Support RJ45 or fiber optic interfaces 2 Fiber optic diagnosis via I C interface per port IRT bridge-delay < 3 s Hardware support for PROFINET protocols including PTCP and LLDP Versatile host interface for serial or parallel connection of external CPUs or local inputs/outputs Small package(15 x 15 mm),1mm ball pitch Application interface The TPS-1 provides 48 General Purpose I/O (GPIO) pins that you can individually configure according to your specific application requirements. 48 GPIO for digital I/Os 8- or 16-bit parallel host interface Serial host interface (SPI Slave) 5GPIO for internal signals (e.g. LEDs) Serial Flash interface The TPS-1 interfaces to an application CPU via the internal shared memory either through the fast SPI slave interface or through the 8- or 16-bit parallel port. ORDERING INFORMATION Part No. Application Package MC-10105F1-821-FNA-M1-A TPS-1 PROFINET IO Device FPBGA 196 Pins 15 x 15 mm The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with our sales representative for availability and additional information. R19DS0069EJ0107 Rev. 1.07 page 1 of 40 th Jul 30 , 2018 TPS-1 INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM The block diagram shows the internal structure and main components of the TPS-1. The additional serial boot Flash component, the oscillator and the physical adaptation for the Ethernet interfaces are not listed. Serial Flash JTAG / Debug (SPI Slave) PROFINET IO CPU Host Interface / Host Interface Parallel - Serial ARM Boot- RAM Parallel Core ROM Interface 8 / 16 Bit 48 GPIO SPI Slave PROFINET IO Core Protocol Handling Status Info LEDs Control Signals IRT Switch Time Sync Clock Signals T1 to T6 LAN signals Clock Power Supply 1.5 V (I2C-bus, link and PHY 1 PHY 2 Unit Switching Regulator Activity), Test Sync Link1, Act1, Link2, Act2 MDI MDI Test Sync 3.3 V 1.0 V 25 MHz R19DS0069EJ0107 Rev. 1.07 page 2 of 40 th Jul 30 , 2018 Shared Memory I/O Interface M U X