Features Datasheet R01DS0363EJ0110 RE01 Group Products with 1.5-Mbyte Flash Memory Rev.1.10 Renesas Microcomputers May 29, 2020 64 MHz, 32-bit Arm Cortex -M0+, 1.5-Mbyte flash memory supporting background operation, 256-Kbyte SRAM, energy harvesting control circuit, MIP LCD controller, 2D graphic engine, 14-bit ultra-low power A/D converter, reference voltage generation circuit, RTC, sub-clock correction circuit (theoretical regulation), security function (optional), USB 2.0 full-speed module, SPI, quad SPI Features Arm Cortex -M0+ core incorporated PLQP0144KA-B 20 20 mm, 0.5-mm pitch Maximum operating frequency: 64 MHz (boost mode) ARM Memory Protection Unit (MPU) PLQP0100KB-B CoreSight debug port: SW-DP 14 14 mm, 0.5-mm pitch Power-saving functions Back-bias control function based on silicon-on-thin-buried-oxide (SOTB) process technology Operation at ultra-low power-supply voltages (from 1.62 V to 3.6 V) SXBG0156MA-A Four power control modes based on the operating frequency 4.5 4.3 mm, 0.3-mm pitch Four low power consumption modes Three power supply modes On-chip code flash memory 1.5-Mbyte code flash memory Background programming/erasing No cycles of waiting for access in operation at or below 32 MHz Various analog circuits one cycle of waiting at frequencies above 32 MHz Single 14-bit successive approximation A/D converter Function for area protection prevents erroneous overwriting or tampering High precision: 7 channels, standard precision: 11 channels Single 12-bit D/A converter with a buffer amplifier On-chip SRAM Single analog comparator (ACMP) 256-Kbyte SRAM with no access wait cycles Single temperature sensor for measuring the internal temperature of the chip Data transfer Reference voltage generation circuit for the 14-bit A/D converter Four DMA controllers Single motor driver control circuit (MTDV) Single data transfer controller (DTC) The MTDV can drive up to three motors. Single constant current (1 mA or 0.5 mA) source circuit with three Reset and supply management channels that can drive three external LEDs Power-on reset circuit (POR) Low voltage detection (LVD) can be set. Various timer circuits Six general PWM timers (GPT) Multiple clock sources Two 32-bit counters External crystal oscillator (main clock): 8 to 32 MHz Four 16-bit counters External crystal oscillator (sub-clock): 32.768 kHz Two asynchronous general-purpose timers (AGT) that can be used in High-speed on-chip oscillator (HOCO): 24, 32, 48, or 64 MHz standby mode Middle-speed on-chip oscillator (MOCO): 2 MHz Two 8-bit timers (TMR) Low-speed on-chip oscillator (LOCO): 32 kHz Single realtime clock (RTC) Independent watchdog timer on-chip oscillator: 16 kHz Single watchdog timer (WDT) PLL frequency synthesizer Single low-speed timer (LST) that operates at 1 kHz Energy harvesting control A circuit for converting hexadecimal numbers to decimal numbers for use as a stopwatch A power generation element is directly connectable. Single low-speed pulse generator (LPG) High-speed startup is possible without having to wait for the charging Pulse output at two frequencies (2.048 or 4.096 kHz) is possible. of a secondary battery. Function to prevent a secondary battery from overcharging Human machine interfaces Single memory-in-pixel (MIP) LCD controller (MLCD) Independent watchdog timer Parallel interface is supported. 14-bit counter, 16-kHz (1/2 LOCO clock frequency) operation Single 2D graphics data conversion circuit (GDT) Sub-clock correction circuit (CCC) Security functions (optional) The CCC corrects the accuracy of oscillation every 16 seconds Single Trusted Secure IP Lite (TSIP-Lite) (theoretical regulation). Events can be generated per second in deep software standby mode. AES (128- or 256-bit key length, supporting ECB, CBC, CMAC, GCM, and others) Communication functions Key wrapping protects against the leakage of the encryption keys Single USB 2.0 full-speed host/function module with PHY layer of users. Two serial peripheral interfaces An access management circuit disables illicit access to the Single 128-bit buffer for which up to eight commands can be specified encryption engine. Single 32-bit buffer for which one command can be specified Using the other security functions together with area protection Single quad serial peripheral interface connectable to an external flash enables secure booting and secure over-the-air (OTA) software memory updates. 2 Two I C bus interfaces Five serial communications interfaces (SCIg) Operating voltage and temperature range 2 Asynchronous, clock-synchronous, simple I C, simple SPI, and smart VCC = IOVCC = 1.62 V to 3.6 V card interfaces, and IrDA interface version 1.0 (the latter is only IOVCCn and AVCCn can each be independently set to a voltage applicable to SCI0) within the range between 1.62 V and 3.6 V. Two serial communication interfaces (SCIi) each having a 16-byte T : 40 to +85C a FIFO R01DS0363EJ0110 Rev.1.10 Page 1 of 151 May 29, 2020RE01 Group Products with 1.5-Mbyte Flash Memory 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 shows the specifications in outline. The specifications in the table are the maximum specifications, and the number of peripheral modules and channels in some cases depends on the number of pins of the package. For details, see Table 1.3, Function Comparison. Table 1.1 Outline of Specifications (1/10) Classification Feature Description CPU Central processing unit Maximum operating frequency: 64 MHz Arm Cortex -M0+ - Revision: r0p1-00rel0 - Arm v6-M architecture profile - Single-cycle integer multiplier Arm Memory Protection Units (MPUs) - Arm v6 Protected Memory System Architecture - Eight protected memory areas SysTick timer - Driven by SYSTICCLK (LOCO clock) or ICLK Memory Code flash memory Maximum 1.5 Mbytes No cycles of waiting for access in operation at or below 32 MHz one cycle of waiting at frequencies above 32 MHz Prefetch function On-board programming (four types): - Programming in serial programming mode (SCI boot mode) - Programming in serial programming mode (USB boot mode) - Programming in on-chip debug mode - Programming by a routine for code flash memory programming within a user program SRAM Maximum 256 Kbytes SRAM0: 2000 0000h to 2000 7FFFh SRAM1: 2000 8000h to 2003 FFFFh Both areas are available during low leakage current mode. 64 MHz, No cycles of waiting for access Startup modes Three startup modes: Normal startup mode Energy harvesting startup mode SCI/USB boot mode Reset The LSI chip supports 12 system resets and one power shutdown reset. System resets RES pin reset Power-on reset Independent watchdog timer reset Watchdog timer reset Voltage monitor 0 reset Voltage monitor 1 reset Voltage monitor BAT reset Bus master MPU error reset Bus slave MPU error reset Stack pointer error reset Software reset Deep software standby reset Power shutdown reset MINPWON mode reset R01DS0363EJ0110 Rev.1.10 Page 2 of 151 May 29, 2020