Datasheet R01DS0368EJ0120 RA4M3 Group Rev.1.20 Renesas Microcontrollers Dec 2, 2020 Leading-performance 100 MHz Arm Cortex-M33 core, up to 1 MB code flash memory with background and SWAP operation, 8 KB Data flash memory, and 128 KB SRAM with Parity/ECC. High-integration with USB 2.0 Full-Speed, SDHI, Quad SPI, and advanced analog. Integrated Secure Crypto Engine with cryptography accelerators, key management support, tamper detection and power analysis resistance in concert with Arm TrustZone for integrated secure element functionality. Features Independent Watchdog Timer (IWDT) Arm Cortex -M33 Core Armv8-M architecture with the main extension Human Machine Interface (HMI) Maximum operating frequency: 100 MHz Capacitive Touch Sensing Unit (CTSU) Arm Memory Protection Unit (Arm MPU) Protected Memory System Architecture (PMSAv8) Multiple Clock Sources Secure MPU (MPU S): 8 regions Non-secure MPU (MPU NS): 8 regions Main clock oscillator (MOSC) (8 to 24 MHz) SysTick timer Sub-clock oscillator (SOSC) (32.768 kHz) Embeds two Systick timers: Secure and Non-secure instance High-speed on-chip oscillator (HOCO) (16/18/20 MHz) Driven by LOCO or system clock Middle-speed on-chip oscillator (MOCO) (8 MHz) Low-speed on-chip oscillator (LOCO) (32.768 kHz) CoreSight ETM-M33 IWDT-dedicated on-chip oscillator (15 kHz) Clock trim function for HOCO/MOCO/LOCO Memory PLL/PLL2 Up to 1-MB code flash memory Clock out support 8-KB data flash memory (100,000 program/erase (P/E) cycles) 128-KB SRAM General-Purpose I/O Ports 5-V tolerance, open drain, input pull-up, switchable driving ability Connectivity Serial Communications Interface (SCI) 6 Operating Voltage Asynchronous interfaces VCC: 2.7 to 3.6 V 8-bit clock synchronous interface Smart card interface Operating Temperature and Packages Simple IIC Simple SPI Ta = -40 to +105 Manchester coding (SCI3, SCI4) 144-pin LQFP (20 mm 20 mm, 0.5 mm pitch) 2 100-pin LQFP (14 mm 14 mm, 0.5 mm pitch) I C bus interface (IIC) 2 64-pin LQFP (10 mm 10 mm, 0.5 mm pitch) Serial Peripheral Interface (SPI) Quad Serial Peripheral Interface (QSPI) USB 2.0 Full-Speed Module (USBFS) Control Area Network module (CAN) 2 SD/MMC Host Interface (SDHI) Serial Sound Interface Enhanced (SSIE) Analog 12-bit A/D Converter (ADC12) 2 12-bit D/A Converter (DAC12) 2 Temperature Sensor (TSN) Timers General PWM Timer 32-bit (GPT32) 4 General PWM Timer 16-bit (GPT16) 4 Low Power Asynchronous General Purpose Timer (AGT) 6 Security and Encryption Secure Crypto Engine 9 Symmetric algorithms: AES Asymmetric algorithms: RSA, ECC, and DSA Hash-value generation: SHA224, SHA256, GHASH 128-bit unique ID Arm TrustZone Up to three regions for the code flash Up to two regions for the data flash Up to three regions for the SRAM Individual secure or non-secure security attribution for each peripheral Device lifecyle management Pin function Up to three tamper pins Secure pin multiplexing System and Power Management Low power modes Battery backup function (VBATT) Realtime Clock (RTC) with calendar and VBATT support Event Link Controller (ELC) Data Transfer Controller (DTC) DMA Controller (DMAC) 8 Power-on reset Low Voltage Detection (LVD) with voltage settings Watchdog Timer (WDT) R01DS0368EJ0120 Rev.1.20 Page 1 of 92 Dec 2, 2020RA4M3 Datasheet 1. Overview 1. Overview The MCU integrates multiple series of software- and pin-compatible Arm -based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development. The MCU in this series incorporates a high-performance Arm Cortex -M33 core running up to 100 MHz with the following features: Up to 1 MB code flash memory 128 KB SRAM Quad Serial Peripheral Interface (QSPI) USBFS, SD/MMC Host Interface Capacitive Touch Sensing Unit (CTSU) Analog peripherals Security and safety features 1.1 Function Outline Table 1.1 Arm core Feature Functional description Arm Cortex-M33 core Maximum operating frequency: up to 100 MHz Arm Cortex-M33 core: Armv8-M architecture with security extension Revision: r0p4-00rel0 Arm Memory Protection Unit (Arm MPU) Protected Memory System Architecture (PMSAv8) Secure MPU (MPU S): 8 regions Non-secure MPU (MPU NS): 8 regions SysTick timer Embeds two Systick timers: Secure and Non-secure instance Driven by SysTick timer clock (SYSTICCLK) or system clock (ICLK) CoreSight ETM-M33 Table 1.2 Memory Feature Functional description Code flash memory Maximum 1 MB of code flash memory. Data flash memory 8 KB of data flash memory. Option-setting memory The option-setting memory determines the state of the MCU after a reset. SRAM On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC). Table 1.3 System (1 of 2) Functional description Operating modes Two operating modes: Single-chip mode SCI/USB boot mode Resets The MCU provides 14 resets. Low Voltage Detection (LVD) The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The detection level can be selected by register settings. The LVD module consists of three separate voltage level detectors (LVD0, LVD1, LVD2). LVD0, LVD1, and LVD2 measure the voltage level input to the VCC pin. LVD registers allow your application to configure detection of VCC changes at various voltage thresholds. R01DS0368EJ0120 Rev.1.20 Page 2 of 92 Dec 2, 2020