SX1212IWLTRT

SX1212 Transceiver Ultra-Low Power Integrated 300-510MHz Transceiver ADVANCED COMMUNICATIONS & SENSING General Description Features The SX1212 is a low cost single-chip transceiver Low Rx power consumption: 3mA operating in the frequency ranges from 300MHz to Low Tx power consumption: 25 mA +10 dBm 510MHz. The SX1212 is optimized for very low power Good reception sensitivity: down to -104 dBm at consumption (3mA in receiver mode). It incorporates a 25 kb/s in FSK, -110 dBm at 2kb/s in OOK baseband modem with data rates up to 150 kb/s. Data Programmable RF output power: up to +12.5 dBm handling features include a sixty-four byte FIFO, in 8 steps packet handling, automatic CRC generation and data Packet handling feature with data whitening and whitening. Its highly integrated architecture allows for automatic CRC generation minimum external component count whilst maintaining RSSI (Received Signal Strength Indicator) design flexibility. All major RF communication Bit rates up to 150 kb/s, NRZ coding parameters are programmable and most of them may On-chip frequency synthesizer be dynamically set. It complies with European (ETSI FSK and OOK modulation EN 300-220 V2.1.1) and North American (FCC part Incoming sync word recognition 15.247 and 15.249) regulatory standards. Built-in Bit-Synchronizer for incoming data and clock synchronization and recovery 5 x 5 mm TQFN package Ordering Information Optimized Circuit Configuration for Low-cost applications Table 1: Ordering Information Minimum Order Applications Part number Delivery Quantity / Multiple Wireless alarm and security systems SX1212IWLTRT Tape & Reel 3000 pieces Wireless sensor networks Automated Meter Reading TQFN-32 package Operating range -40 +85C Home and building automation T refers to Lead Free packaging Industrial monitoring and control This device is WEEE and RoHS compliant Remote Wireless Control Active RFID PHY Application Circuit Schematic Rev 2 June 18th, 2009 Page 1 of 77 www.semtech.com SX1212 ADVANCED COMMUNICATIONS & SENSING Table of Contents 1. General Description ................................................................... 5 5.2.5. Control......................................................................40 1.1. Simplified Block Diagram................................................... 5 5.3. Continuous Mode .............................................................41 5.3.1. General Description .................................................41 1.2. Pin Diagram....................................................................... 6 1.3. Pin Description................................................................... 7 5.3.2. Tx Processing ..........................................................41 2. Electrical Characteristics............................................................ 8 5.3.3. Rx Processing ..........................................................42 2.1. ESD Notice ........................................................................ 8 5.3.4. Interrupt Signals Mapping ........................................42 2.2. Absolute Maximum Ratings............................................... 8 5.3.5. uC Connections........................................................43 5.3.6. Continuous Mode Example ......................................43 2.3. Operating Range ............................................................... 8 2.4. Chip Specification.............................................................. 8 5.4. Buffered Mode ..................................................................44 2.4.1. Power Consumption.................................................. 8 5.4.1. General Description .................................................44 2.4.2. Frequency Synthesis................................................. 9 5.4.2. Tx Processing ..........................................................44 2.4.3. Transmitter ................................................................ 9 5.4.3. Rx Processing ..........................................................45 5.4.4. Interrupt Signals Mapping ........................................46 2.4.4. Receiver .................................................................. 10 2.4.5. Digital Specification................................................. 11 5.4.5. uC Connections........................................................47 3. Architecture Description........................................................... 12 5.4.6. Buffered Mode Example...........................................47 3.1. Power Supply Strategy .................................................... 12 5.5. Packet Mode.....................................................................49 3.2. Frequency Synthesis Description .................................... 13 5.5.1. General Description .................................................49 5.5.2. Packet Format..........................................................49 3.2.1. Reference Oscillator................................................ 13 3.2.2. CLKOUT Output...................................................... 13 5.5.3. Tx Processing ..........................................................51 3.2.3. PLL Architecture...................................................... 14 5.5.4. Rx Processing ..........................................................51 3.2.4. PLL Tradeoffs.......................................................... 14 5.5.5. Packet Filtering ........................................................52 3.2.5. Voltage Controlled Oscillator................................... 15 5.5.6. DC-Free Data Mechanisms......................................53 5.5.7. Interrupt Signal Mapping ..........................................54 3.2.6. PLL Loop Filter........................................................ 16 3.2.7. PLL Lock Detection Indicator .................................. 16 5.5.8. uC Connections........................................................55 3.2.8. Frequency Calculation ............................................ 16 5.5.9. Packet Mode Example .............................................56 3.3. Transmitter Description ................................................... 18 5.5.10. Additional Information ............................................56 3.3.1. Architecture Description .......................................... 18 6. Configuration and Status Registers ..........................................58 6.1. General Description..........................................................58 3.3.2. Bit Rate Setting ....................................................... 19 3.3.3. Alternative Settings ................................................. 19 6.2. Main Configuration Register - MCParam..........................58 3.3.4. Fdev Setting in FSK Mode ...................................... 19 6.3. Interrupt Configuration Parameters - IRQParam ..............60 3.3.5. Fdev Setting in OOK Mode ..................................... 19 6.4. Receiver Configuration parameters - RXParam...............62 3.3.6. Interpolation Filter ................................................... 20 6.5. Sync Word Parameters - SYNCParam.............................63 6.6. Transmitter Parameters - TXParam .................................64 3.3.7. Power Amplifier ....................................................... 20 3.3.8. Common Input and Output Front-End..................... 22 6.7. Oscillator Parameters - OSCParam .................................64 3.4. Receiver Description........................................................ 23 6.8. Packet Handling Parameters PKTParam ......................65 3.4.1. Architecture ............................................................. 23 7. Application Information .............................................................66 3.4.2. LNA and First Mixer ................................................ 24 7.1. Crystal Resonator Specification .......................................66 7.2. Software for Frequency Calculation .................................66 3.4.3. IF Gain and Second I/Q Mixer................................. 24 3.4.4. Channel Filters ........................................................ 24 7.2.1. GUI...........................................................................66 3.4.5. Channel Filters Setting in FSK Mode ...................... 25 7.2.2dll for Automatic Production Bench.........................66 3.4.6. Channel Filters Setting in OOK Mode ..................... 26 7.3. Switching Times and Procedures .....................................66 3.4.7. RSSI........................................................................ 26 7.3.1. Optimized Receive Cycle .........................................67 3.4.8. Fdev Setting in Receive Mode ................................ 28 7.3.2. Optimized Transmit Cycle ........................................68 3.4.9. FSK Demodulator.................................................... 28 7.3.3. Transmitter Frequency Hop Optimized Cycle ..........69 3.4.10. OOK Demodulator................................................. 28 7.3.4. Receiver Frequency Hop Optimized Cycle ..............70 3.4.11. Bit Synchronizer .................................................... 31 7.3.5. Rx Tx and Tx Rx Jump Cycles............................71 3.4.12. Alternative Settings ............................................... 32 7.4. Reset of the Chip..............................................................72 3.4.13. Data Output........................................................... 32 7.4.1. POR .........................................................................72 4. Operating Modes...................................................................... 33 7.4.2. Manual Reset ...........................................................72 4.1. Modes of Operation ......................................................... 33 7.5. Reference Design.............................................................73 4.2. Digital Pin Configuration vs. Chip Mode .......................... 33 7.5.1. Application Schematic..............................................73 5. Data Processing....................................................................... 34 7.5.2. PCB Layout ..............................................................73 7.5.3. Bill Of Material..........................................................74 5.1. Overview.......................................................................... 34 5.1.1. Block Diagram......................................................... 34 8. Packaging Information ..............................................................75 5.1.2. Data Operation Modes ............................................ 34 8.1. Package Outline Drawing .................................................75 5.2. Control Block Description ................................................ 35 8.2. PCB Land Pattern.............................................................75 5.2.1. SPI Interface ........................................................... 35 8.3. Tape & Reel Specification ................................................76 5.2.2. FIFO ........................................................................ 38 9. Revision History ........................................................................77 5.2.3. Sync Word Recognition........................................... 39 10. Contact Information.................................................................77 5.2.4. Packet Handler........................................................ 40 Rev 2 June 18th, 2009 Page 2 of 77 www.semtech.com