Si5327 ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR Features Generates any frequency from 2 kHz Dual clock inputs with manually to 808 MHz from an input frequency controlled hitless switching of 2kHz to 710MHz Free run and VCO freeze modes Ultra-low jitter clock outputs with jitter Support for ITU G.709 and custom generation as low as 0.5 ps rms FEC ratios (255/238, 255/237, (12 kHz20 MHz) 255/236) Integrated loop filter with selectable LOL and LOS alarm outputs 2 loop bandwidth (4 to 525 Hz) I C or SPI programmable Meets OC-192 GR-253-CORE jitter Single 1.8, 2.5, 3.3 V supply specifications Small size: 6 x 6 mm 36-lead QFN Pb-free, ROHS compliant Ordering Information: See page 54. Applications Dual clock outputs with Synchronous Ethernet Pin Assignments programmable signal format Optical modules (LVPECL, LVDS, CML, CMOS) Wireless repeaters/ SONET/SDH OC-48/OC-192/STM- wireless backhaul 16/STM-64 line cards Data converter clocking ITU G.709 and custom FEC line xDSL cards PDH clock synthesis 36 35 34 33 32 31 30 29 28 GbE/10GbE, 1/2/4/8/10G Fibre Test and measurement RST 1 27 SDI NC 2 26 A2 SS Channel line cards Broadcast video INT LOS1 3 25 A1 LOS2 4 24 A0 GND Description VDD 5 23 SDA SDO Pad 6 22 SCL XA XB 7 21 CKSEL The Si5327 is a jitter-attenuating precision clock multiplier for applications GND 8 20 NC NC NC 9 19 requiring sub 1ps jitter performance. The Si5327 accepts two input 10 11 12 13 14 15 16 17 18 clocks ranging from 2 kHz to 710 MHz and generates two output clocks ranging from 2kHz to 808MHz. The two outputs are divided down separately from a common source. The Si5327 can also use its crystal oscillator as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range. The Si5327 input clock frequency and clock multiplication ratio are 2 programmable through an I C or SPI interface. The Si5327 is based on Skyworks Solutions 3rd-generation DSPLL technology, which provides frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5327 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.0 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice August 27, 2021 VDD CMODE RATE CKOUT2+ CKIN2+ CKOUT2 CKIN2 NC NC VDD GND GND CKIN1+ NC CKIN1 CKOUT1 LOL CKOUT1+Si5327 Functional Block Diagram Xtal or Refclock Hitless Switching N31 CKIN1 Mux N1 LS CKOUT1 CKIN2 N32 DSPLL N1 HS CKOUT2 N2 LS Xtal/Refclock N2 Loss of Signal/ VDD (1.8, 2.5, or 3.3 V) Frequency Offset Control Signal Detect GND Loss of Lock 2 I C/SPI Port Clock Select Rate Select Device Interrupt 2 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.0 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice August 27, 2021