Si5380 Rev D Data Sheet Ultra-Low Phase Noise, 12-output JESD204B Clock Generator KEY FEATURES The Si5380 is a high performance, integer-based (M/N) clock generator for small cell DSPLL eliminates external VCXO and applications which demand the highest level of integration and phase noise perform- analog loop filter components th ance. Based on Silicon Laboratories 4 generation DSPLL technology, the Si5380 Supports JESD204B clocking: DCLK and combines frequency synthesis and jitter attenuation in a highly integrated digital solu- SYSREF tion that eliminates the need for external VCXO and loop filter components. A low-cost, Ultra-low jitter of 65 fs fixed-frequency crystal provides frequency stability for free-run and holdover modes. Input frequency range: This all-digital solution provides superior performance that is highly immune to external External Crystal: 54 MHz board disturbances such as power supply noise. Differential: 11.52 MHz to 737.28 MHz LVCMOS: 11.52 MHz to 245.76 MHz Applications: Output frequency range: Differential: 480 kHz to 1.47456 GHz JESD204B clock generation LVCMOS: 480 kHz to 245.76 MHz Remote Radio Units (RRU), Remote Access Networks (RAN), picocells, small cells Status monitoring Wireless base stations (3G, GSM, W-CDMA, 4G/LTE, LTE-A) Hitless switching Remote Radio Head (RRH), wireless repeaters, wireless backhaul Si5380: 4 input, 12 output, 64-QFN 99 mm Data conversion sampling clocks (ADC, DAC, DDC, DUC) 54 MHz XTAL XA XB INT OUT0A OSC OUT0 INT Delay IN0 INT INT OUT1 INT OUT2 IN1 INT DSPLL Delay 4 Input INT OUT3 Clocks INT IN2 INT OUT4 Delay Device and INT OUT5 IN3/FB IN INT System Clocks INT OUT6 Delay INT OUT7 INT OUT8 Status Flags Status Monitor Delay INT OUT9 I2C / SPI Control NVM INT OUT9A Si5380 silabs.com Smart. Connected. Energy-friendly. Rev. 1.0 Not Recommended for New DesignsSi5380 Rev D Data Sheet Feature List 1. Feature List The Si5380-D features are listed below: Digital frequency synthesis eliminates external VCXO and an- Adjustable output-output delay: 68 ps/step, 128 steps alog loop filter components Optional Zero Delay mode Supports JESD204B clocking: DCLK and SYSREF Independent output clock supply pins: 3.3, 2.5, or 1.8 V Ultra-low jitter: Core voltage: 65 fs typ (12 kHz to 20 MHz) VDD = 1.8 V 5% Input frequency range: VDDA = 3.3 V 5% Differential: 11.52 MHz to 737.28 MHz Automatic free-run, lock, and holdover modes LVCMOS: 11.52 MHz to 245.76 MHz Programmable jitter attenuation bandwidth: 0.1 Hz to 100 Hz Output frequency range: Hitless input clock switching Differential: up to 1.47456 GHz Status monitoring (LOS, OOF, LOL) LVCMOS: up to 245.76 MHz Serial interface: I2C or SPI In-circuit programmable with non- Phase noise floor: 159 dBc/Hz volatile OTP memory Spur performance: 103 dBc max (relative to a 122.88 MHz TM ClockBuilder Pro software tool simplifies device configura- carrier) tion Configurable outputs: Si5380: 4 input, 12 output, 64-QFN 99 mm Signal swing: 200 to 3200 mVpp Temperature range: 40 to +85 C Compatible with LVDS, LVPECL Pb-free, RoHS-6 compliant LVCMOS 3.3, 2.5, or 1.8 V Output-output skew using same N-divider: 65 ps (Max) silabs.com Smart. Connected. Energy-friendly. Rev. 1.0 1 Not Recommended for New Designs