SL28EB717 Not Recommended for New Designs EProClock Generator for Intel Tunnel Creek & Top Cliff 14.318MHz output Features Buffered Reference Clock 25MHz Compliant Intel CK505 Clock spec 25MHz Crystal Input or Clock input Low power push-pull type differential output buffers Support Wake-On-LAN (WOL) Integrated resistors on differential clocks EProClock Programmable Technology Wireless friendly 3-bits slew rate control on 2 I C support with readback capabilities single-ended clocks. Triangular Spread Spectrum profile for maximum Differential CPU clocks with selectable frequency electromagnetic interference (EMI) reduction 100MHz Differential SRC clocks o o Industrial Temperature -40 C to 85 C 75MHz Differential SATA clocks 3.3V Power supply 96MHz Differential DOT clock 48-pin QFN package 48MHz USB clock CPU SRC SATA75 DOT96 48M 48M/12M 33M 25M 14.318M Selectable 12 or 48MHz output x2/x3 x3/5 x0/x1 x 1 x1/2 x1 x2 x1 x1 Block Diagram Pin Configuration XIN Crystal/ REF 1:0 CLKIN XOUT CPU PLL 1 Divider (SSC) SRC FS C:A PCI CPU STP PLL 4 Divider (non-SSC) 12 11 10 9 8 7 65 43 21 SATA75M / SRC0 ITP EN PCIF / ITP EN** 13 48 XIN / CLKIN CLKREQ 3** 14 47 XOUT 12M 48M / SEL12 48* 15 PCI/SRC STP * 46 PCI/SRC STP DOT96 PLL 3 VDD 48 16 45 CPU STP * Divider (non-SSC) 17 48M / FSA** 44 SDATA CLKREQ 3:1 48M GND 48 18 43 SCLK DOT96 19 42 GND CPU 20 41 DOT96 CPU0 SEL SATA75 12 / 48M PLL 2 FSB** 21 CPU0 Divider 40 (non-SSC) GND SATA 22 39 VDD CPU 23 SEL 12 48 SATA75M / SRC0 38 CPU1 SATA75M / SRC0 24 37 CPU1 14.318M 25 26 27 28 29 30 31 32 33 34 35 36 OTP SCLK SDATA Logic Core VR CLKPWRGD/ PD * Internal 100K-ohm pull-up resistor ** Internal 100K-ohm pull down resistor DOC : SP-AP-0755 (Rev. AA) Page 1 of 22 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com Not Recommended for New Designs VDD SATA VDD PCI SRC1 GND PCI SRC1 PCI0 / SEL SATA75** SRC2 CLKREQ 2** SRC2 CLKREQ 1** SRC3 GND 14 SRC3 14M / FSC** GND SRC VDD 14 VDD SRC CKPWRGD / WOL STP / PD VDD SRC VDD SUSPEND CPU2 / SRC6 25MHz CPU2 / SRC6 GND SUSPEND SL28EB717 32-QFN Pin Definitions Pin No. Name Type Description 1 GND SUSPEND GND Ground for REF clock and WOL support 2 25MHz O 25MHz reference output clock 3 VDD SUSPEND PWR 3.3V Power Supply for REF clock and power to support WOL CKPWRGD/WOL STP /PD 4 I 3.3V LVTTL input. This pin is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled / Asynchronous active low input pin that stops all outputs except free running 25MHz when WOL EN = 1 (Byte 1 bit 1) This pin becomes a real-time active low input for asserting power down (PD ) when WOL EN = 0 (Byte 1 bit 1). 5 VDD 14 PWR 3.3V Power supply for 14.318MHz clock 6 14.318M / FSC** I/O, PD Fixed 14.318MHz clock output/3.3V-tolerant input for CPU frequency selection (internal 100K-ohm pull-down) Refer to DC Electrical Specifications table for Vil FS and Vih FS specifications. 7 GND 14 GND Ground for 14.318MHz clock 8 CLKREQ 1** I, PD 3.3V clock request input (internal 100K-ohm pull-down) 9 CLKREQ 2** I, PD 3.3V clock request input (internal 100K-ohm pull-down) 10 PCI0 / SEL SATA75** I/O, SE 33MHz clock output/3.3V LVTTL input to enable 75MHz SATA (internal 100K-ohm PD pull-down) 0 = SATA75/SRC0 = 100MHz, 1 = SATA75/SRC0 = 75MHz 11 GND PCI GND Ground for PCI clocks 12 VDD PCI PWR 3.3V Power supply for PCI clocks 13 PCIF / ITP EN** I/O, SE, 33 MHz free running clock output/3.3V LVTTL input to enable SRC6 or CPU2 ITP PD (sampled on the CKPWRGD assertion) 0= SRC6, 1= CPU2 14 CLKREQ 3** I, PD 3.3V clock request input (internal 100K-ohm pull-down) 15 12 48M / SEL12 48* I/O, SE 12 MHz/ 48MHz Clock output/3.3V-tolerance input for 12MHz or 48MHz selection PU (Sampled at CKPWRGD assertion) (internal 100K-ohm pull-up) 0 = 48M, 1 = 12M 16 VDD 48 PWR 3.3V Power supply for 48MHz clocks 17 48M / FSA** I/O Fixed 48 MHz clock output/3.3V-tolerant input for CPU frequency selection PD (internal 100K-ohm pull-down) Refer to DC Electrical Specifications table for Vil FS and Vih FS specifications. 18 GND 48 GND Ground for 48MHz clocks 19 DOT96 O, DIF Fixed true 96MHz clock output 20 DOT96 O, DIF Fixed complement 96MHz clock output 21 FSB** I, PD 3.3V-tolerant input for CPU frequency selection (internal 100K-ohm pull-down) Refer to DC Electrical Specifications table for Vil FS and Vih FS specifications. 22 GND SATA GND Ground for SATA clock 23 SATA75M / SRC0 O, DIF 75MHz or 100MHz True differential serial reference clock 24 SATA75M / SRC0 O, DIF 75MHz or 100MHz Complement differential serial reference clock 25 VDD SATA PWR 3.3V Power supply for SATA clock 26 SRC1 O, DIF 100MHz True differential serial reference clock 27 SRC1 O, DIF 100MHz Complement differential serial reference clock 28 SRC2 O, DIF 100MHz True differential serial reference clock 29 SRC2 O, DIF 100MHz Complement differential serial reference clock 30 SRC3 O, DIF 100MHz True differential serial reference clock 31 SRC3 O, DIF 100MHz Complement differential serial reference clock DOC : SP-AP-0755 (Rev. AA) Page 2 of 22 Not Recommended for New Designs