SL28PCIe14 PCI-Express Gen 2 & Gen 3 Clock Generator & Fan-out Buffer with EProClock Technology Four PCI-Express Gen2 & Gen 3 Clocks Features 25MHz Crystal Input or Clock input PCI-Express Gen 2 & Gen 3 Compliant EProClock Programmable Technology Low power push-pull type differential output buffers 2 I C support with readback capabilities Integrated resistors on differential clocks Triangular Spread Spectrum profile for maximum HW Selectable Buffered Input or crystal synthesizer electromagnetic interference (EMI) reduction mode o o Industrial Temperature -40 C to 85 C Dedicated Output Enable pin for all clocks 3.3V Power supply HW Selectable Frequency and Spread Control 32-pin QFN package Block Diagram Pin Configuration Crystal/ XIN CLKIN XOUT PLL 1 Divider (SSC) SS 1:0 SRC 3:0 DIFFIN DIFFIN OE SRC 3:0 IN SEL EProClock Technology SCLK VR Logic Core SDATA PD * Internal 100K-ohm pull-upresistor ** Internal 100K-ohm pull-down resistor Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 1 Rev. 0.2 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 5, 2021 SL28PCIe14 32-QFN Pin Definitions Pin No. Name Type Description 1 VDD PWR 3.3V Power Supply 2 SS0** I, PD Freqency/Spread Control. Default SS 1:0 =00. (internal 100K-ohm pull-down) 3 SS1** I, PD SS1 SS0 Frequency Spread Note 0 0 100M OFF Default 0 1 100M -0.5% 1 0 100M -/+0.25 1 1 100M -0.75% MID 0 125MHz OFF MID 1 200MHz OFF 4 IN SEL* I, PU 3.3V input to select between crystal input or external differential buffer input mode. 0 = Synthesizer mode, 1=Fan-out Buffer mode (internal 100K-ohm pull-up switching is not glitchless) 5 VSS GND Ground 6 OE SRC0* I,PU 3.3V input to enabled SRC0 clock. (internal 100K-ohm pull-up) 7 OE SRC1* I,PU 3.3V input to enabled SRC1 clock. (internal 100K-ohm pull-up) 8 VDD PWR 3.3V Power Supply 9 OE SRC2* I,PU 3.3V input to enabled SRC2 clock. (internal 100K-ohm pull-up) 10 VSS GND Ground 11 SRC0 O, DIF 100MHz True differential serial reference clock 12 SRC0 O, DIF 100MHz Complement differential serial reference clock 13 SRC1 O, DIF 100MHz True differential serial reference clock 14 SRC1 O, DIF 100MHz Complement differential serial reference clock 15 VDD PWR 3.3V Power Supply 16 VSS GND Ground 17 SRC2 O, DIF 100MHz Complement differential serial reference clock 18 SRC2 O, DIF 100MHz True differential serial reference clock 19 SRC3 O, DIF 100MHz Complement differential serial reference clock 20 SRC3 O, DIF 100MHz True differential serial reference clock 21 VSS GND Ground 22 VDD PWR 3.3V Power Supply 23 OE SRC3* I,PU 3.3V input to enabled SRC3 clock. (internal 100K-ohm pull-up) 24 SCLK I SMBus compatible SCLOCK 25 SDATA I/O SMBus compatible SDATA 26 CKPWRGD/PD * I,PU 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the SS 1:0 . After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for asserting power down (active LOW) 27 VDD PWR 3.3V Power Supply 28XOUT O25.00MHz Crystal output, Float XOUT if using only CLKIN (Clock input) 29 XIN / CLKIN I 25.00MHz Crystal input or 3.3V, 25MHz Clock Input 30 DIFFIN I True differential serial reference clock input 31 DIFFIN I Complement differential serial reference clock 32 VSS GND Ground Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 2 Rev. 0.2 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 5, 2021