S35ML02G300WHI000 SkyHigh Memory

S35ML01G3 S35ML02G3 S35ML04G3 1Gb/2Gb/4Gb, 3V, SPI SLC NAND Flash Memory for Embedded Distinctive Characteristics Density NAND Flash interface 1Gb / 2Gb / 4G b Supports Serial Peripheral Interface (SPI) Architecture Supply Voltage Page size: 3.3-V device: V = 2.7 V ~ 3.6 V CC 1 Gb : (20 48 + 64) bytes 64-byte spare area 1 Gb : (2048 + 128) bytes 128-byte spare area Security 2 Gb /4 Gb: (2048 + 128) bytes 128-byte spare area One Time Programmable (OTP) area Block size: 64 Pages Serial number (unique ID) (Contact factory for support) 1 Gb : 128 KB + 4 KB Hardware program/erase disabled during power transition 1 Gb : 128 KB + 8 KB Volatile and Permanent Block Protection 2 Gb / 4 Gb: 128 KB + 8 KB Plane size Additiona l feature s 1 Gb: 1024 blocks per plane or (128 MB + 4 MB) On- chip ECC correctio n Program an d Eras e 1 Gb: 1024 blocks per plane or (128 MB + 8 MB) Supports single I/O, Dual I/O, Quad I/O 2 Gb: 1024 blocks per plane or (128 MB + 8 MB) Support Frequency up to 104MHZ 4 Gb: 2048 blocks per plane or (256 MB + 16 MB) Supports Clock Polarity and phase modes 0 and 3 Device Size Electronic signatur e 1 Gb: 1 plane per device or 128 Mbyte 2 Gb: 2 planes per device or 256 Mbyte Manufacturer ID: 01h 4 Gb: 2 planes per device or 512 Mbyte Operating temperature Performance Industrial: 40 C to 85 C Page Read / Program Industrial Plus: 40 C to 105 C Read Page Time (tR): 45 s (Typ) Package options Program time: 350 s (Typ) Pb-free and low halogen Block Erase 8-Pin LGA 6 8 m m Block Erase time: 4.0 m s (Typ ) 16-Pin SOIC 300 mi ls Reliability 24-Ball FBGA 8 6 mm 80,000 Program / Erase cycles (Typ) 10 Year Data Retention (Typ) Blocks 0-7 are good at the time of shipment SkyHigh Memory Limited Suite 4401-02, 44/F One Island East, www.skyhighmemory.com Document Number: 002-19205 Rev. H 18 Westlands Road Hong Kong ReReRevised Sept. 14 vised Mvised Nov. 16 2021ay 28 20202211 S35ML01G3 S35ML02G3 S35ML04G3 Contents 1. General Description ...................................................... 3 6. Timing Diagrams ......................................................... 36 1.1 Logic Diagram ................................................................. 4 6.1 SPI Clock Timing.......................................................... 36 1.2 Connection Diagram ........................................................ 5 6.2 Serial Input Timing..........................................................36 6.3 Serial Output Timing.................................................... 36 1.3 Pin Description ................................................................ 6 1.4 Block Diagram ................................................................. 6 6.4 WP Timing................................................................. 37 1.5 Array Organization .......................................................... 7 6.5 HOLD Timing............................................................. 37 1.6 Memory Ad dre................................ssing .................................... 9 6.6 Block Erase/Program Execute/ Page read Timing ......... 38 2. Bus Operation .............................................................10 6.7 Read Buffer 1X (03h or 0Bh Timing ...) .......................................... 38 2.1 SPI Modes...................................................................10 6.8 Fast Read Dual Output Buffer 2X (3Bh) Timing............. 39 2.2 SPI Protocol................................................................. 10 6.9 Fast Read Quad Output Buffer 2X (6Bh) Timing........... 39 3. Command Set ..............................................................11 6.10 Program Load 1X (02h) and Program Load Random 3.1 Power up and Reset Commands .................................... 13 Data 1X (84h) buffer Timing........................................... 4 0 3.2 Write Enable and Write Disable Commands................... 13 6.11 Quad Program Data Load 4X (32h) and Quad Program 3.3 Hardware Write Protection............................................. 41 13 Load Random Data 1X (34h) buffer Timing.................... 3.4 Read Operation.............................................................. 13 6.12 ...................... 41 Small Data Input. Guidelines.................... 3.5 Page Program Operation...............................................13 6.13 Fast Read Dual IO 2X(BBh)-Timing............................. 42 3.6 Feature Operations ........................................................... 14 6.14 Fast Read Quad I/O 4X (EBh) Timing......................... 43 3.6.1 Set Feature ................................................................... 14 6.15 Power-up Timing.......................................................... 44 3.6. 2 Get Feature.................................................................... 14 7. Physical Interface ........................................................ 45 3.7 Feature Registers......................................................... 15 7.1 Physical Diagrams .......................................................... 45 3.8 Read ID........................................................................18 Error Management ....................................................... 48 8. 3.9 Read Unique ID.............................................................. 18 System Bad Block Replacement ................................... 48 8.1 3.10 One Time Programming OTP.......................................18 Bad Block Management ................................................ 49 8.2 3.10.1Read OTP 18 .................................................................... Ordering Information ........................................................ 50 18 9. 3.10.2Program OTP ................................................................ Document History ....................................................... 51 10. 3.10. 3OTP Program Prevention........................................... 19 3.11 Internal Data Move......................................................... 19 3.12 Read Parameter Page.............................................................20 (84h ) Buff er Timi ng Diagr am 4. Electrical Characteristics ..........................................23 4.1 Valid Blocks ................................................................. 23 4.2 Absolute Maximum Ratings ...........................................23 4.3 Recommended Operating Conditions............................23 4.4 AC Test Conditions........................................................ 23 4.5 AC Characteristics ......................................................... 24 4.6 DC Characteristics ........................................................ 26 4.7 Pin Capacitance ........................................................... 27 4.8 Program / Erase Characteristics.................................... 27 5. Security Features ........................................................28 5.1 27 Volatile Block Protection Overview ................................ 5.2 Permanent Block Protection Overview ...........................................33 5.3 Permanent Block Protection Lock-Down Sequence ............................35 5.4 Block Protection Status Command............................... 35 5.5 Block Lock Status Register ......................................................... 35 Document Number: 002-19205 Rev. H Page 2 of 51