74VHC273 OCTAL D-TYPE FLIP FLOP WITH CLEAR HIGH SPEED: f = 165 MHz (TYP.) at V = 5V MAX CC LOW POWER DISSIPATION: I = 4 A (MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V = V = 28% V (MIN.) NIH NIL CC SOP TSSOP POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: I = I = 8 mA (MIN) OH OL Table 1: Order Codes BALANCED PROPAGATION DELAYS: t t PLH PHL PACKAGE T & R OPERATING VOLTAGE RANGE: SOP 74VHC273MTR V (OPR) = 2V to 5.5V CC TSSOP 74VHC273TTR PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 273 IMPROVED LATCH-UP IMMUNITY When the CLEAR input is held low, the Q outputs LOW NOISE: V = 0.9V (MAX.) are held low independently of the other inputs. OLP Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no DESCRIPTION regard to the supply voltage. This device can be The 74VHC273 is an advanced high-speed used to interface 5V to 3V. CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR All inputs and outputs are equipped with fabricated with sub-micron silicon gate and 2 protection circuits against static discharge, giving double-layer metal wiring C MOS technology. them 2KV ESD immunity and transient excess Information signals applied to D inputs are voltage. transferred to the Q outputs on the positive going edge of the clock pulse. Figure 1: Pin Connection And IEC Logic Symbols Rev. 5 November 2004 1/1474VHC273 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N SYMBOL NAME AND FUNCTION 1CLEAR Asynchronous Master Reset (Active LOW) 2, 5, 6, 9, 12, Q0 to Q7 Flip-Flop Outputs 15, 16,19 3, 4, 7, 8, 13, D0 to D7 Data Inputs 14, 17, 18 11 CLOCK Clock Input (LOW-to-HIGH Edge Triggered) 10 GND Ground (0V) 20 V Positive Supply Voltage CC Table 3: Truth Table INPUTS OUTPUT FUNCTION CLEAR DB Q L X X L CLEAR HL L HH H Q HX NO CHANGE n X : Dont Care Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays 2/14