M48T35AV 3.3 V, 256 Kbit (32 Kbit x 8) TIMEKEEPER SRAM Features Integrated, ultra low power SRAM, real-time clock, power-fail control circuit and battery BYTEWIDE RAM-like clock access BCD coded year, month, day, date, hours, minutes, and seconds 28 1 Battery low flag (BOK) Frequency test output for real-time clock PCDIP28 Automatic power-fail chip deselect and WRITE battery/crystal protection CAPHAT WRITE protect voltage (V = power-fail deselect voltage): PFD SNAPHAT M48T35AV: V = 3.0 to 3.6 V CC battery/crystal 2.7 V V 3.0 V PFD Self-contained battery and crystal in the CAPHAT DIP package SOIC package provides direct connection for a SNAPHAT housing containing the battery and crystal SNAPHAT housing (battery and crystal) is 28 replaceable 1 Pin and function compatible with JEDEC standard 32 Kbit x 8 SRAMs SOH28 RoHS compliant Lead-free second level interconnect June 2011 Doc ID 6845 Rev 9 1/29 www.st.com 1Contents M48T35AV Contents 1 Description . 5 2 Operation modes 8 2.1 READ mode 8 2.2 WRITE mode 10 2.3 Data retention mode . 11 3 Clock operations . 13 3.1 Reading the clock . 13 3.2 Setting the clock 13 3.3 Stopping and starting the oscillator . 13 3.4 Calibrating the clock . 14 3.5 Century bit 15 3.6 V noise and negative going transients . 17 CC 4 Maximum ratings . 18 5 DC and AC parameters 19 6 Package mechanical data 22 7 Part numbering 26 8 Environmental information . 27 9 Revision history . 28 2/29 Doc ID 6845 Rev 9