M48T37Y-70MH1E

M48T37Y M48T37V 5.0 or 3.3 V, 256 Kbit (32 Kbit x 8) TIMEKEEPER SRAM Features Integrated ultra low power SRAM, real-time SNAPHAT (SH) clock, power-fail control circuit, and battery Battery/crystal Frequency test output for real-time clock software calibration Automatic power-fail chip deselect and WRITE protection Watchdog timer WRITE protect voltage (V = Power-fail deselect voltage): PFD M48T37Y: V = 4.5 to 5.5 V CC 44 4.2 V V 4.5 V PFD 1 M48T37V: V = 3.0 to 3.6 V CC 2.7 V V 3.0 V PFD SOH44 (MH) 44-pin SOIC Packaging includes a 44-lead SOIC and SNAPHAT top (to be ordered separately) SOIC package provides direct connection for a SNAPHAT top which contains the battery and crystal Microprocessor power-on reset (valid even during battery backup mode) Programmable alarm output active in the battery backup mode Battery low flag RoHS compliant Lead-free second level interconnect August 2010 Doc ID 7019 Rev 9 1/30 www.st.com 1Contents M48T37Y, M48T37V Contents 1 Description . 5 2 Operation modes 8 2.1 READ mode 8 2.2 WRITE mode 10 2.3 Data retention mode . 11 3 Clock operations . 12 3.1 Reading the clock . 12 3.2 Setting the clock 12 3.3 Stopping and starting the oscillator . 12 3.4 Setting the alarm clock . 14 3.5 Calibrating the clock . 15 3.6 Watchdog timer 16 3.7 Power-on reset . 17 3.8 Programmable interrupts . 17 3.9 Battery low flag . 18 3.10 Initial power-on defaults 18 3.11 V noise and negative going transients . 18 CC 4 Maximum ratings . 20 5 DC and AC parameters 21 6 Package mechanical data 24 7 Part numbering 27 8 Environmental information . 28 9 Revision history . 29 2/30 Doc ID 7019 Rev 9