M74HC138B1R

M74HC138 3 TO 8 LINE DECODER (INVERTING) HIGH SPEED: t = 13ns (TYP.) at V = 6V PD CC LOW POWER DISSIPATION: I = 4A(MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V = V = 28 % V (MIN.) NIH NIL CC DIP SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 4mA (MIN) OH OL BALANCED PROPAGATION DELAYS: t t ORDER CODES PLH PHL WIDE OPERATING VOLTAGE RANGE: PACKAGE TUBE T & R V (OPR) = 2V to 6V CC DIP M74HC138B1R PIN AND FUNCTION COMPATIBLE WITH SOP M74HC138M1R M74HC138RM13TR 74 SERIES 138 TSSOP M74HC138TTR DESCRIPTION The M74HC138 is an high speed CMOS 3 TO 8 inhibited and all the 8 outputs go high. Three LINE DECODER fabricated with silicon gate enable inputs are provided to ease cascade 2 C MOS technology. connection and application of address decoders If the device is enabled, 3 binary select inputs (A, for memory systems. B, and C) determine which one of the outputs will All inputs are equipped with protection circuits go low. If enable input G1 is held low or either G2A against static discharge and transient excess or G2B is held high, the decoding function is voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/10M74HC138 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1, 2, 3 A, B, C Address Inputs 4, 5 G2A, G2B Enable Inputs 6 G1 Enable Input 9, 10, 11, 12, Y0 to Y7 Data Outputs 13, 14, 15, 7 8 GND Ground (0V) 16 V Positive Supply Voltage CC TRUTH TABLE INPUTS OUTPUTS ENABLE SELECT G2B G2A G1 CBA Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X L X X X HHHHH HHH XH XXXX HHHHH HHH HXXXXX HHHHH HHH LL H LLLL HHHH HHH L LHL LH HLH H H H H H L LHLHLH HLH H H H H L L H L HHHHH L H HHH L L HH L L HHHH L HHH L L HH L HHHHHH L H H L L HHH L HHHHH H L H L L HHHHHHHHH HH L X : Dont Care LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/10