SCLT3-8BT8 STMicroelectronics

SCLT3-8BQ7, SCLT3-8BT8 Datasheet High speed digital input current limiter with digital filter Features 8 inputs - 8-bit SPI output High side input with common ground 5 V voltage regulator QFN 7x7 - 48L Package: QFN 7x7 - 48L or HTSSOP-38 35 V reverse polarity capable Adjustable current limiters LED output for visual status Optional: 16-bit mode with parity check, temperature and voltage alarms HTSSOP-38 package 48 47 46 45 44 43 42 41 40 39 38 37 Daisy chain capable 36 1 Input digital filter with adjustable delay: 20 s to 3 ms 2 35 3 34 4 33 Power dissipation: 78 mW per channel 5 32 31 6 Complies with the following standards: 7 30 8 29 IEC 61000-4-2: 9 28 10 27 26 8 kV (contact discharge) 11 12 25 15 kV (air discharge) 13 14 15 16 17 18 19 20 21 22 23 24 Top view IEC 61000-4-4: Input: 1 kV Power supply: 2.5 kV Applications Product status link Programmable logic controller and remote input modules SCLT3-8BQ7, SCLT3-8BT8 High speed protected termination for digital input with serialized SPI output IEC61131-2 type 1, 2 and 3 Description The SCLT3 series provides an 8-line protected digital input termination with serialized state transfer. This device enhances the I/O module density by cutting the dissipation (78 mW per input) and reducing the count of opto-transistors. An adjustable digital filter and an LED driver are embedded in each type 3 input section. Its 2 MHz SPI peripheral output serializes the input state transfer to the I/O module controller. DS11042 - Rev 5 - January 2022 www.st.com For further information contact your local STMicroelectronics sales office.SCLT3-8BQ7, SCLT3-8BT8 Circuit block diagrams 1 Circuit block diagrams Figure 1. Circuit block diagram V DD VV IN Protected input 1 DDDD MISOMISO V R LD /MIS/MISOO 1 V <V IN R 8 lines 8 lines COMCOM S VV DDDD WRITE COM P SHIFT MOSIMOSI CAPTURE SCSCKK IN I MOSI /CS/CS SHIFT 7 lines LD SPMSPM I 16-bit 4 lines VV CC Power Power REF Current supply reset reference DVR V DD VV CSCS Under voltage OSC Over temperature 8 / 64 Oscillator Clock divider alarm alarm Figure 2. Basic application schematic ACPL-K73L ACPL-W70L V DD2 V DD LED6 DVR LED7 R OSC OSC LED8 SPM COM P COM P R PD V V V V V V V V V CC I1 I2 I3 I4 I5 I6 I7 I8 DS11042 - Rev 5 page 2/20 Protected input I=2t o8 R C V C /CS R S V CS SCK 16 s / 3 ms digital filters COM MOSI P R I IN1 R I IN2 MISO Parity Input state register 8 lines bits gen. R I COM S IN3 R R I REF IN4 REF COM P LED1 Control state register Data state register R I IN5 LED2 R I LED3 IN6 R I IN7 LED4 Transfer R I logic IN8 LED5