SPC56EL60x, SPC56EL54x, SPC564L60x, SPC564L54x 32-bit Power Architecture microcontroller for automotive SIL3/ASILD chassis and safety applications Datasheet - production data Replicated junction temperature sensor Non-maskable interrupt (NMI) 16-region memory protection unit (MPU) LQFP100 (14 x 14x 1.4 mm) Clock monitoring units (CMU) LQFP144 (20 x 20 x 1.4 mm) Power management unit (PMU) Cyclic redundancy check (CRC) unit LFBGA257 (14 x 14 mm) Decoupled Parallel mode for high-performance use of replicated cores Nexus Class 3+ interface Features Interrupts High-performance e200z4d dual core Replicated 16-priority controller 32-bit Power Architecture technology CPU Replicated 16-channel eDMA controller Core frequency as high as 120 MHz GPIOs individually programmable as input, output or special function Dual issue five-stage pipeline core Three 6-channel general-purpose eTimer units Variable Length Encoding (VLE) 2 FlexPWM units Memory Management Unit (MMU) Four 16-bit channels per module 4 KB instruction cache with error detection Communications interfaces code 2 LINFlexD channels Signal processing engine (SPE) 3 DSPI channels with automatic chip select Memory available generation 1 MB flash memory with ECC 2 FlexCAN interfaces (2.0B Active) with 32 128 KB on-chip SRAM with ECC message objects Built-in RWW capabilities for EEPROM FlexRay module (V2.1 Rev. A) with 2 emulation channels, 64 message buffers and data SIL3/ASILD innovative safety concept: rates up to 10 Mbit/s LockStep mode and Fail-safe protection Two 12-bit analog-to-digital converters (ADCs) Sphere of replication (SoR) for key 16 input channels components (such as CPU core, eDMA, Programmable cross triggering unit (CTU) crossbar switch) to synchronize ADCs conversion with timer Fault collection and control unit (FCCU) and PWM Redundancy control and checker unit Sine wave generator (D/A with low pass filter) (RCCU) on outputs of the SoR connected On-chip CAN/UART bootstrap loader to FCCU Boot-time Built-In Self-Test for Memory Single 3.0 V to 3.6 V voltage supply (MBIST) and Logic (LBIST) triggered by Ambient temperature range 40 C to 125 C hardware Junction temperature range 40 C to 150 C Boot-time Built-In Self-Test for ADC and flash memory triggered by software July 2015 DocID15457 Rev 12 1/165 This is information on a product in full production. www.st.comContents SPC56ELx, SPC564Lx Contents 1 Introduction 7 1.1 Document overview 7 1.2 Description . 7 1.3 Device comparison . 8 1.4 Block diagram 10 1.5 Feature details . 14 1.5.1 High-performance e200z4d core 14 1.5.2 Crossbar switch (XBAR) 15 1.5.3 Memory Protection Unit (MPU) . 15 1.5.4 Enhanced Direct Memory Access (eDMA) 15 1.5.5 On-chip flash memory with ECC 16 1.5.6 On-chip SRAM with ECC 16 1.5.7 Platform flash memory controller 17 1.5.8 Platform Static RAM Controller (SRAMC) . 17 1.5.9 Memory subsystem access time 18 1.5.10 Error Correction Status Module (ECSM) 18 1.5.11 Peripheral bridge (PBRIDGE) 19 1.5.12 Interrupt Controller (INTC) . 19 1.5.13 System clocks and clock generation . 20 1.5.14 Frequency-Modulated Phase-Locked Loop (FMPLL) 21 1.5.15 Main oscillator 21 1.5.16 Internal Reference Clock (RC) oscillator 21 1.5.17 Clock, reset, power, mode and test control modules (MC CGM, MC RGM, MC PCU, and MC ME) . 22 1.5.18 Periodic Interrupt Timer Module (PIT) 22 1.5.19 System Timer Module (STM) . 22 1.5.20 Software Watchdog Timer (SWT) . 22 1.5.21 Fault Collection and Control Unit (FCCU) . 23 1.5.22 System Integration Unit Lite (SIUL) 23 1.5.23 Non-Maskable Interrupt (NMI) 23 1.5.24 Boot Assist Module (BAM) . 23 1.5.25 System Status and Configuration Module (SSCM) 24 1.5.26 FlexCAN 24 1.5.27 FlexRay . 25 2/165 DocID15457 Rev 12