ST72334J/N, ST72314J/N, ST72124J 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES Memories 8K or 16K Program memory (ROM or single voltage FLASH) with read-out protection and in-situ programming (remote ISP) 256 bytes EEPROM Data memory (with read- out protection option in ROM devices) 384 or 512 bytes RAM Clock, Reset and Supply Management PSDIP42 PSDIP56 Enhanced reset system Enhanced low voltage supply supervisor with 3 programmable levels Clock sources: crystal/ceramic resonator os- cillators or RC oscillators, external clock, backup Clock Security System 4 Power Saving Modes: Halt, Active-Halt, Wait and Slow Beep and clock-out capabilities TQFP64 TQFP44 Interrupt Management 14 x 14 10 x 10 10 interrupt vectors plus TRAP and RESET 15 external interrupt lines (4 vectors) 44 or 32 I/O Ports 1 Analog Peripheral 44 or 32 multifunctional bidirectional I/O lines: 8-bit ADC with 8 input channels (6 only on 21 or 19 alternate function lines ST72334Jx, not available on ST72124J2) 12 or 8 high sink outputs 4 Timers Instruction Set Configurable watchdog timer 8-bit data manipulation Realtime base 63 basic instructions Two 16-bit timers with: 2 input captures (only 17 main addressing modes one on timer A), 2 output compares (only one 8 x 8 unsigned multiply instruction on timer A), External clock input on timer A, PWM and Pulse generator modes True bit manipulation 2 Communications Interfaces SPI synchronous serial interface Development Tools SCI asynchronous serial interface (LIN com- Full hardware/software development package patible) Device Summary Features ST72124J2 ST72314J2 ST72314J4 ST72314N2 ST72314N4 ST72334J2 ST72334J4 ST72334N2 ST72334N4 Program memory - bytes 8K 8K 16K 8K 16K 8K 16K 8K 16K RAM (stack) - bytes 384 (256) 384 (256) 512 (256) 384 (256) 512 (256) 384 (256) 512 (256) 384 (256) 512 (256) EEPROM - bytes - - - -- 256 256 256 256 Watchdog, Two 16-bit Timers, SPI, SCI Peripherals -ADC Operating Supply 3.2V to 5.5V CPU Frequency Up to 8 MHz (with up to 16 MHz oscillator) Operating Temperature -40C to +85C (-40C to +105/125C optional) Packages TQFP44 / SDIP42 TQFP64 / SDIP56 TQFP44 / SDIP42 TQFP64 / SDIP56 Rev. 2.5 April 2003 1/153 1Table of Contents 1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION . 5 2 INTRODUCTION 6 3 PIN DESCRIPTION 7 4 REGISTER & MEMORY MAP . 13 5 FLASH PROGRAM MEMORY 17 5.1 INTRODUCTION . 17 5.2 MAIN FEATURES 17 5.3 STRUCTURAL ORGANISATION 17 5.4 IN-SITU PROGRAMMING (ISP) MODE . 17 5.5 MEMORY READ-OUT PROTECTION 17 6 DATA EEPROM . 18 6.1 INTRODUCTION . 18 6.2 MAIN FEATURES 18 6.3 MEMORY ACCESS . 19 6.4 POWER SAVING MODES . 20 6.5 ACCESS ERROR HANDLING 20 6.6 REGISTER DESCRIPTION . 21 7 DATA EEPROM Register Map and Reset Values 22 7.1 READ-OUT PROTECTION OPTION 22 8 CENTRAL PROCESSING UNIT . 23 8.1 INTRODUCTION . 23 8.2 MAIN FEATURES 23 8.3 CPU REGISTERS 23 9 SUPPLY, RESET AND CLOCK MANAGEMENT 26 9.1 LOW VOLTAGE DETECTOR (LVD) 27 9.2 RESET SEQUENCE MANAGER (RSM) . 28 9.3 MULTI-OSCILLATOR (MO) . 30 9.4 CLOCK SECURITY SYSTEM (CSS) 31 9.5 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION . 32 10 INTERRUPTS 33 10.1 NON MASKABLE SOFTWARE INTERRUPT . 33 10.2 EXTERNAL INTERRUPTS . 33 10.3 PERIPHERAL INTERRUPTS . 33 11 POWER SAVING MODES 35 11.1 INTRODUCTION . 35 11.2 SLOW MODE . 35 11.3 WAIT MODE 36 11.4 ACTIVE-HALT AND HALT MODES 37 12 I/O PORTS . 39 12.1 INTRODUCTION . 39 153 12.2 FUNCTIONAL DESCRIPTION 39 12.3 I/O PORT IMPLEMENTATION 42 2/153 2