ST72F260G1M6

ST72260Gx, ST72262Gx, ST72264Gx 8-BIT MCU WITH FLASH OR ROM MEMORY, 2 ADC, TWO 16-BIT TIMERS, I C, SPI, SCI INTERFACES Memories 4 K or 8 Kbytes Program memory: ROM or Single voltage extended Flash (XFlash) with read-out protection write protection and In- Circuit Programming and In-Application Pro- gramming (ICP and IAP). 10K write/erase cy- cles guaranteed, data retention: 20 years at 55C. 256 bytes RAM SDIP32 Clock, Reset and Supply Management Enhanced reset system Enhanced low voltage supply supervisor (LVD) with 3 programmable levels and auxil- iary voltage detector (AVD) with interrupt ca- SO28 LFBGA 6x6mm pability for implementing safe power-down procedures Clock sources: crystal/ceramic resonator os- Two 16-bit timers with: 2 input captures, 2 out- cillators, internal RC oscillator and bypass for put compares, external clock input on one tim- external clock er, PWM and Pulse generator modes PLL for 2x frequency multiplication 3 Communication Interfaces Clock-out capability SPI synchronous serial interface 4 Power Saving Modes: Halt, Active Halt,Wait 2 I C multimaster interface (SMBus V1.1 Com- and Slow pliant) Interrupt Management SCI asynchronous serial interface Nested interrupt controller 1 Analog peripheral 10 interrupt vectors plus TRAP and RESET 10-bit ADC with 6 input channels 22 external interrupt lines (on 2 vectors) Instruction Set 22 I/O Ports 8-bit data manipulation 22 multifunctional bidirectional I/O lines 63 basic instructions with illegal opcode de- 20 alternate function lines tection 8 high sink outputs 17 main addressing modes 4 Timers 8 x 8 unsigned multiply instruction Main Clock Controller with Real time base and Development Tools Clock-out capabilities Full hardware/software development package Configurable watchdog timer Device Summary Features ST72260G1 ST72262G1 ST72262G2 ST72264G1 ST72264G2 Program memory - bytes 4K 4K 8K 4K 8K RAM (stack) - bytes 256 (128) Watchdog timer, RTC, Watchdog timer, RTC, Watchdog timer, RTC, Peripherals 2 Two16-bit timers, SPI Two 16-bit timers, SPI, ADC Two 16-bit timers, SPI, SCI, I C, ADC Operating Supply 2.7 V to 5.5 V CPU Frequency Up to 8 MHz (with oscillator up to 16 MHz) PLL 4/8 MHz 0 C to +70 C / Operating Temperature -40 C to +85 C -40 C to +85 C -40 C to +85 C Packages SO28 / SDIP32 SO28 / SDIP32 LFBGA Rev. 3 June 2005 1/172 1 Obsolete Product(s) - Obsolete Product(s)Table of Contents 1 INTRODUCTION 5 2 PIN DESCRIPTION 6 3 REGISTER & MEMORY MAP . 10 4 FLASH PROGRAM MEMORY 14 4.1 INTRODUCTION . 14 4.2 MAIN FEATURES 14 4.3 PROGRAMMING MODES 14 4.4 ICC INTERFACE . 15 4.5 MEMORY PROTECTION 16 4.6 RELATED DOCUMENTATION 16 4.7 REGISTER DESCRIPTION . 16 5 CENTRAL PROCESSING UNIT . 17 5.1 INTRODUCTION . 17 5.2 MAIN FEATURES 17 5.3 CPU REGISTERS 17 6 SUPPLY, RESET AND CLOCK MANAGEMENT 20 6.1 PHASE LOCKED LOOP . 20 6.2 MULTI-OSCILLATOR (MO) . 21 6.3 RESET SEQUENCE MANAGER (RSM) . 22 6.4 SYSTEM INTEGRITY MANAGEMENT (SI) 24 7 INTERRUPTS . 28 7.1 INTRODUCTION . 28 7.2 MASKING AND PROCESSING FLOW 28 7.3 INTERRUPTS AND LOW POWER MODES 30 7.4 CONCURRENT & NESTED MANAGEMENT . 30 7.5 INTERRUPT REGISTER DESCRIPTION 31 8 POWER SAVING MODES . 33 8.1 INTRODUCTION . 33 8.2 SLOW MODE . 33 8.3 WAIT MODE 34 8.4 ACTIVE-HALT AND HALT MODES 35 8.5 HALT MODE 36 9 I/O PORTS 38 9.1 INTRODUCTION . 38 9.2 FUNCTIONAL DESCRIPTION 38 9.3 I/O PORT IMPLEMENTATION 41 9.4 UNUSED I/O PINS . 41 9.5 LOW POWER MODES 41 9.6 INTERRUPTS . 41 9.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION . 42 172 9.8 I/O PORT REGISTER DESCRIPTION 43 10 MISCELLANEOUS REGISTERS . 45 2/172 2 Obsolete Product(s) - Obsolete Product(s)