ST72F521R9T6

ST72F521, ST72521B 80/64-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, 2 FIVE TIMERS, SPI, SCI, I C, CAN INTERFACE Memories 32K to 60K dual voltage High Density Flash (HDFlash) or ROM with read-out protection capability. In-Application Programming and In-Circuit Programming for HDFlash devices 1K to 2K RAM HDFlash endurance: 100 cycles, data reten- tion: 20 years at 55C Clock, Reset And Supply Management TQFP64 14 x 14 Enhanced low voltage supervisor (LVD) for TQFP64 main supply and auxiliary voltage detector TQFP80 10 x 10 (AVD) with interrupt capability 14 x 14 Clock sources: crystal/ceramic resonator os- cillators, internal RC oscillator and bypass for external clock PLL for 2x frequency multiplication Four power saving modes: Halt, Active-Halt, 4 Communications Interfaces Wait and Slow SPI synchronous serial interface Interrupt Management SCI asynchronous serial interface Nested interrupt controller 2 I C multimaster interface 14 interrupt vectors plus TRAP and RESET (SMbus V1.1 compliant) Top Level Interrupt (TLI) pin CAN interface (2.0B Passive) 15 external interrupt lines (on 4 vectors) Analog periperal (low current coupling) Up to 64 I/O Ports 10-bit ADC with 16 input robust input ports 48 multifunctional bidirectional I/O lines 34 alternate function lines Instruction Set 16 high sink outputs 8-bit Data Manipulation 5 Timers 63 Basic Instructions Main Clock Controller with: Real time base, 17 main Addressing Modes Beep and Clock-out capabilities 8 x 8 Unsigned Multiply Instruction Configurable watchdog timer Development Tools Two 16-bit timers with: 2 input captures, 2 out- put compares, external clock input on one tim- Full hardware/software development package er, PWM and pulse generator modes In-Circuit Testing capability 8-bit PWM Auto-Reload timer with: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector Device Summary Features ST72F521(M/R/AR)9 ST72F521(R/AR)6 ST72521B(M/R/AR)9 ST72521B(R/AR)6 Program memory - bytes Flash 60K Flash 32K ROM 60K ROM 32K RAM (stack) - bytes 2048 (256) 1024 (256) 2048 (256) 1024 (256) Operating Voltage 3.8V to 5.5V Temp. Range up to -40C to +125 C TQFP80 14x14 (M), TQFP80 14x14 (M), TQFP64 14x14 (R), TQFP64 TQFP64 14x14 (R), TQFP64 Package TQFP64 14x14 (R), TQFP64 14x14 (R), 10x10 (AR) 10x10 (AR) TQFP64 10x10 (AR) TQFP64 10x10 (AR) Rev. 5 May 2005 1/215 1Table of Contents 1 INTRODUCTION . 7 2 PIN DESCRIPTION 8 3 REGISTER & MEMORY MAP . 14 4 FLASH PROGRAM MEMORY 18 4.1 INTRODUCTION 18 4.2 MAIN FEATURES . 18 4.3 STRUCTURE . 18 4.3.1 Read-out Protection 18 4.4 ICC INTERFACE 19 4.5 ICP (IN-CIRCUIT PROGRAMMING) . 20 4.6 IAP (IN-APPLICATION PROGRAMMING) . 20 4.7 RELATED DOCUMENTATION . 20 4.7.1 Register Description . 20 5 CENTRAL PROCESSING UNIT . 21 5.1 INTRODUCTION 21 5.2 MAIN FEATURES . 21 5.3 CPU REGISTERS . 21 6 SUPPLY, RESET AND CLOCK MANAGEMENT 24 6.1 PHASE LOCKED LOOP 24 6.2 MULTI-OSCILLATOR (MO) 25 6.3 RESET SEQUENCE MANAGER (RSM) 26 6.3.1 Introduction 26 6.3.2 Asynchronous External RESET pin 26 6.3.3 External Power-On RESET 27 6.3.4 Internal Low Voltage Detector (LVD) RESET 27 6.3.5 Internal Watchdog RESET 27 6.4 SYSTEM INTEGRITY MANAGEMENT (SI) 28 6.4.1 Low Voltage Detector (LVD) . 28 6.4.2 Auxiliary Voltage Detector (AVD) . 29 6.4.3 Low Power Modes 31 6.4.4 Register Description . 32 7 INTERRUPTS . 33 7.1 INTRODUCTION 33 7.2 MASKING AND PROCESSING FLOW . 33 7.3 INTERRUPTS AND LOW POWER MODES . 35 7.4 CONCURRENT & NESTED MANAGEMENT 35 7.5 INTERRUPT REGISTER DESCRIPTION . 36 7.6 EXTERNAL INTERRUPTS 38 7.6.1 I/O Port Interrupt Sensitivity 38 7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . 40 8 POWER SAVING MODES . 42 8.1 INTRODUCTION 42 215 8.2 SLOW MODE . 42 8.3 WAIT MODE . 43 2/215 1