ST7260xx Low speed USB 8-bit MCU family with up to 8K Flash and serial communications interface Features Memories 4 or 8 Kbytes program memory: high density Flash (HDFlash), or FastROM with QFN40 SO24 readout and write protection (6x6) In-application programming (IAP) and in- circuit programming (ICP) 2 very high sink true open drain I/Os (25 384 bytes RAM memory (128-byte stack) mA at 1.5 V) Clock, reset and supply management Up to 8 lines with interrupt capability Run, Wait, Slow and Halt CPU modes 2 timers 12 or 24 MHz oscillator Programmable Watchdog RAM Retention mode 16-bit Timer with 2 Input Captures, 2 Optional low voltage detector (LVD) Output Compares, PWM output and clock input USB (Universal Serial Bus) interface Communications interface DMA for low speed applications compliant with USB 1.5 Mbs (version 2.0) and HID Asynchronous serial communications specifications (version 1.0) interface (SCI) Integrated 3.3 V voltage regulator and Instruction set transceivers 63 basic instructions Supports USB DFU class specification 17 main addressing modes Suspend and Resume operations 8 x 8 unsigned multiply instruction 3 Endpoints with programmable In/Out Development tools configuration Versatile development tools including , Up to 19 I/O ports software library, hardware emulator, Up to 8 high sink I/Os (10 mA at 1.3 V) programming boards, HID and DFU software layer Table 1. Device summary Features ST7260K2 ST7260K1 ST7260E2 ST7260E1 Flash program memory - 8 K4 K8 K 4 K bytes RAM (stack) - bytes 384 (128) Peripherals Watchdog timer, 16-bit timer, USB, SCI Operating supply 4.0 V to 5.5 V CPU frequency 8 MHz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator) Operating temperature 0 C to +70 C Packages QFN40 (6x6) SO24 February 2009 Rev 3 1/139 www.st.com 139Contents ST7260xx Contents 1 Description . 7 2 Block diagram 8 3 Pin description . 9 4 Register & memory map . 14 5 Flash program memory . 17 5.1 Introduction . 17 5.2 Main features 17 5.3 Structure 17 5.3.1 Readout protection 18 5.4 ICC interface 19 5.5 ICP (in-circuit programming) 20 5.6 IAP (in-application programming) . 20 5.7 Related documentation 20 5.7.1 Flash control/status register (FCSR) . 20 6 Central processing unit (CPU) 21 6.1 Introduction . 21 6.2 Main features 21 6.3 CPU registers 21 6.3.1 Accumulator (A) . 22 6.3.2 Index registers (X and Y) 22 6.3.3 Program counter (PC) 22 6.3.4 Condition code register (CC) . 22 6.3.5 Stack pointer register (SP) . 24 7 Reset and clock management 25 7.1 Reset 25 7.2 Low voltage detector (LVD) . 25 7.2.1 Watchdog reset . 25 7.2.2 External reset . 25 2/139