STA339BWS13TR

STA339BWS 2.1-channel 40-watt high-efficiency digital system Sound Terminal Datasheet - production data Two independent DRCs configurable as a 2 dual-band anticlipper (B DRC) or as independent limiters/compressors EQ-DRC for DRC based on filtered signals Dedicated LFE processing for bass boosting Audio presets: 15 preset crossover filters 5 preset anticlipping modes PowerSSO-36 Preset nighttime listening mode with exposed pad down (EPD) Individual channel soft/hard mute Independent channel volume and DSP bypass 2 I S input data interface Input and output channel mapping Features Automatic invalid input-detect mute Wide-range supply voltage, 4.5 V to 21.5 V Up to 8 user-programmable biquads/channel Three power output configurations: Three coefficient banks for storing EQ presets 2 channels of ternary PWM (2 x 20 W into 2 with fast recall via I C interface 8 at 18 V) + PWM output Bass/treble tones and de-emphasis control 2 channels of ternary PWM (2 x 20 W into Selectable high-pass filter for DC blocking 8 at 18 V) + ternary stereo line-out 2.1 channels of binary PWM (left, right, Advanced AM interference frequency LFE) (2 x 9 W into 4 +1 x 20 W into 8 switching and noise suppression modes at 18 V) Selectable high- or low-bandwidth FFX with 100-dB SNR and dynamic range noise-shaping topologies Scalable FFX modulation index Selectable clock input ratio Selectable 32- to 192-kHz input sample rates 96-kHz internal processing sample rate 2 I C control with selectable device address Thermal overload and short-circuit protection technology Digital gain/attenuation +48dB to -80dB with 0.5-dB/step resolution Video apps: 576 x f input mode supported S Soft volume update with programmable ratio Pin and SW compatible with STA333BW, STA339BW, STA559BW and STA559BWS Individual channel and master gain/attenuation Table 1. Device summary Order code Package Packing STA339BWS13TR PowerSSO-36 EPD Tape and reel January 2019 DocID015276 Rev 9 1/79 This is information on a product in full production. www.st.comContents STA339BWS Contents 1 Description . 8 2 Pin connections 10 2.1 Connection diagram . 10 2.2 Pin description . 10 3 Electrical specifications . 12 3.1 Absolute maximum ratings 12 3.2 Thermal data 12 3.3 Recommended operating conditions 13 3.4 Electrical specifications for the digital section . 13 3.5 Electrical specifications for the power section . 14 3.6 Power on/off sequence . 16 4 Serial audio interface . 17 4.0.1 Timings . 17 4.0.2 Delay serial clock enable 17 4.0.3 Channel input mapping . 17 5 Processing data paths 18 2 6I C bus specification 20 6.1 Communication protocol 20 6.1.1 Data transition or change 20 6.1.2 Start condition 20 6.1.3 Stop condition 20 6.1.4 Data input . 20 6.2 Device addressing 20 6.3 Write operation . 21 6.3.1 Byte write 21 6.3.2 Multi-byte write 21 6.4 Read operation . 21 6.4.1 Current address byte read . 21 2/79 DocID015276 Rev 9