STCD22x0, STCD23x0, STCD24x0 Multichannel clock distribution circuit Features 2, 3 or 4 output buffered clock distribution Single-ended square wave (or sine wave) clock input Rail-to-rail (0 V to VTCXO) square wave output Individual enable pin for each output 1.8 V, high PSRR LDO for external clock source voltage supply (VTCXO) No AC coupling capacitor needed Ultra-low phase noise and standby current Flip Chip (12-bump, 16-bump) Common system clock request, open drain, active low Clock enable signal polarities factory programmable (STCD23x0) Option pins allow clock enable polarities to be Applications user configurable (STCD22x0 and STCD24x0) Multimode RF clock reference High isolation output-to-output & output-to-input Baseband peripheral device clock reference 2.5 V to 5.1 V battery supply voltage Mobile Internet Devices (MIDs) 40 pF max load driving capability per output Available in chip scale package (CSP) Operating temperature : 20 C to 85 C Table 1. Device summary Reference Part number Channels Enable polarity Package Flip Chip 12-bump (1) STCD22x0 STCD2200 2-channel (1.2 mm x 1.6 mm) User program STCD2400 Flip Chip 16-bump STCD24x0 4-channel (1) (1.6 mm x 1.6 mm) STCD2410 (1) STCD2300 (1) STCD2310 Flip Chip 12-bump STCD23x0 3-channel Factory program (1) (1.2 mm x 1.6 mm) STCD2320 (1) STCD2330 1. Contact local ST sales office for availability. January 2010 Doc ID 15400 Rev 2 1/39 www.st.com 1Contents STCD22x0, STCD23x0, STCD24x0 Contents 1 Description . 5 2 Device overview 6 3 Device operation . 12 3.1 Operation . 12 3.2 Enable polarity . 13 4 Application information . 14 4.1 LDO input capacitor . 14 4.2 LDO output capacitor 14 4.3 LDO BYP pin 14 4.4 MC pin 14 REQ 4.5 Phase noise . 15 4.6 Jitter . 16 4.7 Output trace line 16 4.8 Typical application connections 17 5 Typical operating characteristics . 19 6 Maximum ratings . 27 7 DC and AC parameters 28 8 Package mechanical data 31 9 Part numbering 37 10 Revision history . 38 2/39 Doc ID 15400 Rev 2