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STDRIVE101 Datasheet Triple half-bridge gate driver Features Operating voltage from 5.5 to 75 V 600 mA sink/source current capability 3.3 V and 5 V control logic Two input strategies: ENx/INx with adjustable deadtime generation INHx/INLx with interlocking Matched propagation delay for all channels Very short propagation delay: 40 ns Integrated bootstrap diodes 12 V LDO linear regulator (50 mA max.) Embedded V monitor for each external MOSFET DS Overcurrent comparator UVLO and thermal shutdown protection Standby mode for low current consumption operation Application Home automation and appliances e-bikes Power tools Fans and pumps Product status link Industrial automation STDRIVE101 Textile machines Product label Gaming and consoles Description The STDRIVE101 is a low voltage gate driver suitable for driving three-phase brushless motors. It is a single-chip with three half-bridge gate drivers for N-channel power MOSFETs. Each driver has a current capability of 600 mA (sink/source). It integrates a low drop linear regulator generating the supply voltage for both low-side and high-side gate drivers through a bootstrap circuitry. The device provides Under Voltage Lock Out (UVLO) on both the low-side and high- side sections, preventing the power switches from operating in low efficiency or dangerous conditions. The control logic integrated into the STDRIVE101 allows two input strategies (high- side and low-side or enable and PWM driving signals). The driving method is selected according to DT/MODE pin. In both cases, prevention from cross conduction is ensured by interlocking or internally generated deadtime. The STDRIVE101 also features a V monitoring protection for each external DS MOSFET, thermal shutdown and can be put in the standby mode to reduce the power consumption. The device is available in a VFQFPN 4x4 24 leads package option. DS13472 - Rev 1 - October 2020 www.st.com For further information contact your local STMicroelectronics sales office.STDRIVE101 Block diagram 1 Block diagram Figure 1. STDRIVE101 block diagram 12V VM + V CC 12 V LDO Reg STBY V V V CC BOOT SCREF + SCREF Half-bridge 1 BOOT1 V DSth GHS1 DT/MODE HS + OUT1 IN3/INH3 - V CC + IN2/INH2 - GLS1 IN1/INH1 LS + V DSth EN3/INL3 BOOT2 GHS2 EN2/INL2 OUT2 Half-bridge 2 M EN1/INL1 GLS2 BOOT3 VDD GHS3 Half-bridge 3 nFAULT OUT3 GLS3 CP + V REF - DS13472 - Rev 1 page 2/32 REG12 VS Decoding logic and dead-time GND