STM32F105xx STM32F107xx Connectivity line, ARM -based 32-bit MCU with 64/256 KB Flash, USB OTG, Ethernet, 10 timers, 2 CANs, 2 ADCs, 14 communication interfaces Datasheet - production data Features FBGA Core: ARM 32-bit Cortex -M3 CPU 72 MHz maximum frequency, 1.25 LQFP100 14 14 mm LFBGA100 10 10 mm DMIPS/MHz (Dhrystone 2.1) performance LQFP64 10 10 mm at 0 wait state memory access Up to 10 timers with pinout remap capability Single-cycle multiplication and hardware division Up to four 16-bit timers, each with up to 4 Memories IC/OC/PWM or pulse counter and 64 to 256 Kbytes of Flash memory quadrature (incremental) encoder input 64 Kbytes of general-purpose SRAM 1 16-bit motor control PWM timer with dead-time generation and emergency stop Clock, reset and supply management 2 watchdog timers (Independent and 2.0 to 3.6 V application supply and I/Os Window) POR, PDR, and programmable voltage SysTick timer: a 24-bit downcounter detector (PVD) 2 16-bit basic timers to drive the DAC 3-to-25 MHz crystal oscillator Internal 8 MHz factory-trimmed RC Up to 14 communication interfaces with pinout remap capability Internal 40 kHz RC with calibration Up to 2 I2C interfaces (SMBus/PMBus) 32 kHz oscillator for RTC with calibration Up to 5 USARTs (ISO 7816 interface, LIN, Low power IrDA capability, modem control) Sleep, Stop and Standby modes Up to 3 SPIs (18 Mbit/s), 2 with a VBAT supply for RTC and backup registers multiplexed I2S interface that offers audio 2 12-bit, 1 s A/D converters (16 channels) class accuracy via advanced PLL schemes Conversion range: 0 to 3.6 V 2 CAN interfaces (2.0B Active) with 512 Sample and hold capability bytes of dedicated SRAM Temperature sensor USB 2.0 full-speed device/host/OTG controller with on-chip PHY that supports HNP/SRP/ID up to 2 MSPS in interleaved mode with 1.25 Kbytes of dedicated SRAM 2 12-bit D/A converters 10/100 Ethernet MAC with dedicated DMA DMA: 12-channel DMA controller and SRAM (4 Kbytes): IEEE1588 hardware Supported peripherals: timers, ADCs, DAC, support, MII/RMII available on all packages I2Ss, SPIs, I2Cs and USARTs Table 1. Device summary Debug mode Serial wire debug (SWD) & JTAG interfaces Reference Part number Cortex -M3 Embedded Trace Macrocell STM32F105R8, STM32F105V8 Up to 80 fast I/O ports STM32F105xx STM32F105RB, STM32F105VB STM32F105RC, STM32F105VC 51/80 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant STM32F107RB, STM32F107VB STM32F107xx STM32F107RC, STM32F107VC CRC calculation unit, 96-bit unique ID March 2017 DocID15274 Rev 10 1/108 This is information on a product in full production. www.st.comContents STM32F105xx, STM32F107xx Contents 1 Introduction 9 2 Description 10 2.1 Device overview 10 2.2 Full compatibility throughout the family 12 2.3 Overview . 13 2.3.1 ARM Cortex-M3 core with embedded Flash and SRAM 14 2.3.2 Embedded Flash memory . 14 2.3.3 CRC (cyclic redundancy check) calculation unit 14 2.3.4 Embedded SRAM . 14 2.3.5 Nested vectored interrupt controller (NVIC) 14 2.3.6 External interrupt/event controller (EXTI) . 15 2.3.7 Clocks and startup . 15 2.3.8 Boot modes 15 2.3.9 Power supply schemes . 16 2.3.10 Power supply supervisor 16 2.3.11 Voltage regulator 16 2.3.12 Low-power modes . 16 2.3.13 DMA 17 2.3.14 RTC (real-time clock) and backup registers 17 2.3.15 Timers and watchdogs 18 2.3.16 IC bus 19 2.3.17 Universal synchronous/asynchronous receiver transmitters (USARTs) . 19 2.3.18 Serial peripheral interface (SPI) . 20 2 2.3.19 Inter-integrated sound (I S) 20 2.3.20 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 20 2.3.21 Controller area network (CAN) . 21 2.3.22 Universal serial bus on-the-go full-speed (USB OTG FS) . 21 2.3.23 GPIOs (general-purpose inputs/outputs) 21 2.3.24 Remap capability 22 2.3.25 ADCs (analog-to-digital converters) 22 2.3.26 DAC (digital-to-analog converter) . 22 2.3.27 Temperature sensor 23 2.3.28 Serial wire JTAG debug port (SWJ-DP) . 23 2/108 DocID15274 Rev 10