STM32F303xD STM32F303xE ARM Cortex -M4 32b MCU+FPU, up to 512KB Flash, 80KB SRAM, FSMC, 4 ADCs, 2 DAC ch., 7 comp, 4 Op-Amp, 2.0-3.6 V Datasheet - production data Features Core: ARM Cortex -M4 32-bit CPU with 72 MHz FPU, single-cycle multiplication and LQFP100 LQFP144 HW division, 90 DMIPS (from CCM), DSP LQFP64 (14 14 mm) (20 x 20 mm) (10 10 mm) instruction and MPU (memory protection unit) Operating conditions: V , V voltage range: 2.0 V to 3.6 V DD DDA Memories UFBGA100 WLCSP100 Up to 512 Kbytes of Flash memory (4.775 x 5.041 mm) (7 x 7 mm) 64 Kbytes of SRAM, with HW parity check Two 12-bit DAC channels with analog supply implemented on the first 32 Kbytes. from 2.4 to 3.6 V Routine booster: 16 Kbytes of SRAM on Seven ultra-fast rail-to-rail analog comparators instruction and data bus, with HW parity with analog supply from 2.0 to 3.6 V check (CCM) Four operational amplifiers that can be used in Flexible memory controller (FSMC) for PGA mode, all terminals accessible with static memories, with four Chip Select analog supply from 2.4 to 3.6 V CRC calculation unit Up to 24 capacitive sensing channels supporting Reset and supply management touchkey, linear and rotary touch sensors Power-on/Power-down reset (POR/PDR) Up to 14 timers: Programmable voltage detector (PVD) One 32-bit timer and two 16-bit timers with Low-power modes: Sleep, Stop and up to four IC/OC/PWM or pulse counter Standby and quadrature (incremental) encoder input V supply for RTC and backup registers BAT Three 16-bit 6-channel advanced-control Clock management timers, with up to six PWM channels, 4 to 32 MHz crystal oscillator deadtime generation and emergency stop 32 kHz oscillator for RTC with calibration One 16-bit timer with two IC/OCs, one OCN/PWM, deadtime generation and Internal 8 MHz RC with x 16 PLL option emergency stop Internal 40 kHz oscillator Two 16-bit timers with IC/OC/OCN/PWM, Up to 115 fast I/Os deadtime generation and emergency stop All mappable on external interrupt vectors Two watchdog timers (independent, Several 5 V-tolerant window) Interconnect matrix One SysTick timer: 24-bit downcounter 12-channel DMA controller Two 16-bit basic timers to drive the DAC Four ADCs 0.20 s (up to 40 channels) with Calendar RTC with Alarm, periodic wakeup selectable resolution of 12/10/8/6 bits, 0 to from Stop/Standby 3.6 V conversion range, separate analog Communication interfaces supply from 2.0 to 3.6 V CAN interface (2.0B Active) October 2016 DocID026415 Rev 5 1/173 This is information on a product in full production. www.st.comSTM32F303xD STM32F303xE 2 Three I C Fast mode plus (1 Mbit/s) with USB 2.0 full-speed interface with LPM 20 mA current sink, SMBus/PMBus, support wakeup from STOP Infrared transmitter Up to five USART/UARTs (ISO 7816 SWD, Cortex -M4 with FPU ETM, JTAG interface, LIN, IrDA, modem control) 96-bit unique ID Up to four SPIs, 4 to 16 programmable bit frames, two with multiplexed half/full duplex 2 I S interface Table 1. Device summary Reference Part number STM32F303xD STM32F303RD, STM32F303VD, STM32F303ZD. STM32F303xE STM32F303RE, STM32F303VE, STM32F303ZE. 2/173 DocID026415 Rev 5