STM32H733VG STM32H733ZG Arm Cortex -M7 32-bit 550 MHz MCU, 1 MB Flash, 564 KB RAM, Ethernet, USB, 3x FD-CAN, Graphics, 2x 16-bit ADCs, crypto/hash Datasheet - production data Features Includes ST state-of-the-art patented technology LQFP144 LQFP100 (20x20 mm) (14x14 mm) Core FBGA FBGA 32-bit Arm Cortex -M7 CPU with DP-FPU, L1 cache: 32-Kbyte data cache and 32-Kbyte instruction cache allowing 0-wait state TFBGA100 UFBGA144 execution from embedded Flash memory and (8x8 mm) (7x7 mm) external memories, frequency up to 550 MHz, MPU, 1177 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions Clock, reset and supply management 1.62 V to 3.6 V application supply and I/O Memories POR, PDR, PVD and BOR 1 Mbyte of embedded Flash memory with ECC Dedicated USB power SRAM: total 564 Kbytes all with ECC, including 128 Kbytes of data TCM RAM for critical real- Embedded LDO regulator time data + 432 Kbytes of system RAM (up to Internal oscillators: 64 MHz HSI, 48 MHz 256 Kbytes can remap on instruction TCM HSI48, 4 MHz CSI, 32 kHz LSI RAM for critical real time instructions) + External oscillators: 4-50 MHz HSE, 4 Kbytes of backup SRAM (available in the 32.768 kHz LSE lowest-power modes) Flexible external memory controller with up to Low power 16-bit data bus: SRAM, PSRAM, Sleep, Stop and Standby modes SDRAM/LPSDR SDRAM, NOR/NAND memories V supply for RTC, 3232-bit backup BAT registers 2 x Octo-SPI interface with XiP and on-the-fly decryption support Analog 2 x SD/SDIO/MMC interface 216-bit ADC, up to 3.6 MSPS in 16-bit: up to Bootloader with security services support (SFI 18 channels and 7.2 MSPS in double- and SB-SFU) interleaved mode 1 x 12-bit ADC, up to 5 MSPS in 12-bit, up to 12 Graphics channels Chrom-ART Accelerator graphical hardware 2 x comparators accelerator enabling enhanced graphical user interface to reduce CPU load 2 x operational amplifier GBW = 8 MHz LCD-TFT controller supporting up to XGA 2 12-bit D/A converters resolution December 2021 DS13314 Rev 3 1/236 www.st.comSTM32H733xG Digital filters for sigma delta modulator SWPMI single-wire protocol master I/F (DFSDM) MDIO slave interface 8 channels/4 filters Mathematical acceleration 4 DMA controllers to offload the CPU CORDIC for trigonometric functions acceleration 1 MDMA with linked list support FMAC: Filter mathematical accelerator 2 dual-port DMAs with FIFO 1 basic DMA with request router capabilities Digital temperature sensor 24 timers Cryptographic/HASH acceleration Seventeen 16-bit (including 5 x low power AES 128, 192, 256, TDES, HASH (MD5, SHA- 16-bit timer available in stop mode) and four 1, SHA-2), HMAC 32-bit timers, each with up to 4 IC/OC/PWM or 2x OTFDEC AES-128 in CTR mode for Octo- pulse counter and quadrature (incremental) SPI memory encryption/decryption encoder input 2x watchdogs, 1x SysTick timer True random number generator Debug mode CRC calculation unit SWD and JTAG interfaces RTC with sub-second accuracy and 2-Kbyte embedded trace buffer hardware calendar Up to 114 I/O ports with interrupt ROP, PC-ROP, tamper detection, secure capability firmware upgrade support Up to 35 communication interfaces 96-bit unique ID Up to 5 I2C FM+ interfaces (SMBus/PMBus) All packages are ECOPACK2 compliant Up to 5 USARTs/5 UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1 x LPUART Up to 6 SPIs with 4 with muxed duplex I2S for audio class accuracy via internal audio PLL or external clock and up to 5 x SPI (from 5 x USART when configured in synchronous mode) 2x SAI (serial audio interface) 1 FD/TT-CAN and 2x FD-CAN 8- to 14-bit camera interface 16-bit parallel slave synchronous interface SPDIF-IN interface HDMI-CEC Ethernet MAC interface with DMA controller USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip FS PHY and ULPI for external HS PHY 2/236 DS13314 Rev 3