New Product SiZ904DT Vishay Siliconix Dual N-Channel 30 V (D-S) MOSFETs FEATURES PRODUCT SUMMARY Halogen-free According to IEC 61249-2-21 V (V) R () Max. I (A) Q (Typ.) DS DS(on) D g Definition a TrenchFET Power MOSFETs 0.024 at V = 10 V GS 12 Channel-1 30 3.8 nC 100 % R and UIS Tested a = 4.5 V g 0.030 at V GS 12 Compliant to RoHS Directive 2002/95/EC a 0.0135 at V = 10 V GS 16 Channel-2 30 7.3 nC a 0.017 at V = 4.5 V GS 16 APPLICATIONS Notebook System Power POL Low Current DC/DC PowerPAIR 6 x 5 D 1 Pin 1 G 1 5 mm 1 D 1 2 D1 G 1 3 D D 1 1 N-Channel 1 4 S /D MOSFET 1 2 G 2 S /D 1 2 Pin 9 8 S2 7 6 mm 6 G 2 5 N-Channel 2 MOSFET S Ordering Information: SiZ904DT-T1-GE3 (Lead (Pb)-free and Halogen-free) 2 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A Parameter Symbol Channel-1Channel-2Unit V 30 30 Drain-Source Voltage DS V V 20 Gate-Source Voltage GS a a T = 25 C 12 16 C a a T = 70 C 12 C 16 Continuous Drain Current (T = 150 C) I J D b, c b, c T = 25 C A 9.5 14.5 b, c b, c T = 70 C 7.6 11.6 A A I Pulsed Drain Current (t = 300 s) 30 40 DM a a T = 25 C 12 C 16 Source Drain Current Diode Current I S b, c b, c T = 25 C 3.2 4 A I Single Pulse Avalanche Current 10 15 AS L = 0.1 mH E Single Pulse Avalanche Energy 511 mJ AS T = 25 C 20 33 C T = 70 C 12.9 21 C Maximum Power Dissipation P W D b, c b, c T = 25 C A 3.8 4.8 b, c b, c T = 70 C 2.4 3.1 A T , T Operating Junction and Storage Temperature Range - 55 to 150 J stg C d, e Soldering Recommendations (Peak Temperature) 260 THERMAL RESISTANCE RATINGS Channel-1 Channel-2 Parameter Symbol Unit Typ. Max. Typ. Max. b, f t 10 s R 25 33 20 26 Maximum Junction-to-Ambient thJA C/W Maximum Junction-to-Case (Drain) Steady State R 4.7 6.2 3 3.8 thJC Notes: a. Package limited. b. Surface mounted on 1 x 1 FR4 board. c. t = 10 s. d. See solder profile (www.vishay.com/doc 73257). The PowerPAIR is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under steady state conditions is 68 C/W for Channel-1 and 61 C/W for Channel-2. Document Number: 63482 www.vishay.com S11-2380-Rev. B, 28-Nov-11 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000New Product SiZ904DT Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J Parameter Symbol Test Conditions Min. Typ.Max.Unit Static V = 0 V, I = 250 A Ch-1 30 GS D V Drain-Source Breakdown Voltage V DS V = 0 V, I = 250 A Ch-2 30 GS D I = 250 A Ch-1 35 D V Temperature Coefficient V /T DS DS J I = 250 A Ch-2 33 D mV/C I = 250 A Ch-1 - 4.5 D V Temperature Coefficient V /T GS(th) GS(th) J I = 250 A Ch-2 - 5 D V = V , I = 250 A Ch-1 1 2.5 DS GS D V Gate Threshold Voltage V GS(th) V = V , I = 250 A Ch-2 1.2 2.5 DS GS D Ch-1 100 I V = 0 V, V = 20 V Gate-Body Leakage nA GSS DS GS Ch-2 100 V = 30 V, V = 0 V Ch-1 1 DS GS V = 30 V, V = 0 V Ch-2 1 DS GS I Zero Gate Voltage Drain Current A DSS V = 30 V, V = 0 V, T = 55 C Ch-1 5 DS GS J V = 30 V, V = 0 V, T = 55 C Ch-2 5 DS GS J V 5 V, V = 10 V Ch-1 20 DS GS b I A On-State Drain Current D(on) V 5 V, V = 10 V Ch-2 20 DS GS V = 10 V, I = 7.8 A Ch-1 0.020 0.024 GS D V = 10 V, I = 10 A Ch-2 0.0105 0.0135 GS D b R Drain-Source On-State Resistance DS(on) V = 4.5 V, I = 7 A Ch-1 0.024 0.030 GS D V = 4.5 V, I = 7 A Ch-2 0.0135 0.017 GS D V = 10 V, I = 7.8 A Ch-1 17 DS D b g S Forward Transconductance fs V = 10 V, I = 10 A Ch-2 24 DS D a Dynamic Ch-1 435 C Input Capacitance iss Channel-1 Ch-2 846 V = 15 V, V = 0 V, f = 1 MHz DS GS Ch-1 95 C Output Capacitance pF oss Ch-2 187 Channel-2 Ch-1 42 V = 15 V, V = 0 V, f = 1 MHz DS GS C Reverse Transfer Capacitance rss Ch-2 72 V = 15 V, V = 10 V, I = 7.8 A Ch-1 8 12 DS GS D V = 15 V, V = 10 V, I = 10 A Ch-2 15.4 23 DS GS D Total Gate Charge Q g Ch-1 3.8 6 Channel-1 Ch-2 7.3 11 nC V = 15 V, V = 4.5 V, I = 7.8 A DS GS D Ch-1 1.4 Q Gate-Source Charge gs Ch-2 2.3 Channel-2 Ch-1 1.1 V = 15 V, V = 4.5 V, I = 10 A DS GS D Q Gate-Drain Charge gd Ch-2 2.2 Ch-1 0.6 3.2 6.4 R Gate Resistance f = 1 MHz g Ch-2 0.2 0.8 1.6 Notes: a. Guaranteed by design, not subject to production testing. b. Pulse test pulse width 300 s, duty cycle 2 %. www.vishay.com Document Number: 63482 2 S11-2380-Rev. B, 28-Nov-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000