W94AD6KBHX5I TR Winbond

W94AD6KB / W94AD2KB 1Gb Mobile LPDDR Table of Contents- 1. GENERAL DESCRIPTION ................................................................................................................................. 4 2. FEATURES ........................................................................................................................................................ 4 3. ORDER INFORMATION .................................................................................................................................... 4 4. BALL ASSIGNMENT .......................................................................................................................................... 5 4.1 60VFBGA Ball Assignment: LPDDR x16 .............................................................................................. 5 4.2 90VFBGA Ball Assignment: LPDDR x32 .............................................................................................. 5 5. BALL CONFIGURATION .................................................................................................................................... 6 5.1 Ball Descriptions ................................................................................................................................... 6 5.2 Addressing Table ................................................................................................................................. 7 6. BLOCK DIAGRAM .............................................................................................................................................. 8 6.1 Block Diagram ...................................................................................................................................... 8 6.2 Simplified State Diagram ...................................................................................................................... 9 7. FUNCTIONAL DESCRIPTION ......................................................................................................................... 10 7.1 Initialization ......................................................................................................................................... 10 7.1.1 Initialization Flow Diagram .................................................................................................... 11 7.1.2 Initialization Waveform Sequence ........................................................................................ 12 7.2 Mode Register Set Operation ............................................................................................................. 12 7.3 Mode Register Definition .................................................................................................................... 13 7.3.1 Burst Length ......................................................................................................................... 13 7.3.2 Burst Definition ..................................................................................................................... 14 7.3.3 Burst Type ............................................................................................................................ 15 7.3.4 Read Latency ....................................................................................................................... 15 7.4 Extended Mode Register Description ................................................................................................. 15 7.4.1 Extended Mode Register Definition ...................................................................................... 16 7.4.2 Partial Array Self Refresh ..................................................................................................... 16 7.4.3 Automatic Temperature Compensated Self Refresh ............................................................ 16 7.4.4 Output Drive Strength ........................................................................................................... 16 7.5 Status Register Read ......................................................................................................................... 17 7.5.1 SRR Register Definition........................................................................................................ 17 7.5.2 Status Register Read Timing Diagram ................................................................................. 18 7.6 Commands ......................................................................................................................................... 19 7.6.1 Basic Timing Parameters for Commands ............................................................................. 19 7.6.2 Truth Table Commands ..................................................................................................... 19 7.6.3 Truth Table - DM Operations ................................................................................................ 20 7.6.4 Truth Table CKE ................................................................................................................ 20 7.6.5 Truth Table - Current State Bank n - Command to Bank n ................................................... 21 7.6.6 Truth Table - Current State Bank n, Command to Bank m ................................................... 22 8. OPERATION .................................................................................................................................................... 24 8.1 Deselect ............................................................................................................................................. 24 8.2 No Operation ...................................................................................................................................... 24 8.2.1 NOP Command .................................................................................................................... 24 8.3 Mode Register Set .............................................................................................................................. 25 8.3.1 Mode Register Set Command .............................................................................................. 25 8.3.2 Mode Register Set Command Timing .................................................................................. 25 8.4 Active .................................................................................................................................................. 26 Publication Release Date: Jun. 04, 2018 Revision: A01-006 - 1 - W94AD6KB / W94AD2KB 8.4.1 Active Command .................................................................................................................. 26 8.4.2 Bank Activation Command Cycle ......................................................................................... 27 8.5 Read ................................................................................................................................................... 27 8.5.1 Read Command ................................................................................................................... 27 8.5.2 Basic Read Timing Parameters ............................................................................................ 28 8.5.3 Read Burst Showing CAS Latency ....................................................................................... 29 8.5.4 Read to Read ....................................................................................................................... 29 8.5.5 Consecutive Read Bursts ..................................................................................................... 29 8.5.6 Non-Consecutive Read Bursts ............................................................................................. 30 8.5.7 Random Read Bursts ........................................................................................................... 31 8.5.8 Read Burst Terminate .......................................................................................................... 31 8.5.9 Read to Write ....................................................................................................................... 32 8.5.10 Read to Precharge ............................................................................................................... 33 8.5.11 Burst Terminate of Read ...................................................................................................... 34 8.6 Write ................................................................................................................................................... 34 8.6.1 Write Command ................................................................................................................... 34 8.6.2 Basic Write Timing Parameters ............................................................................................ 35 8.6.3 Write Burst (min. and max. tDQSS) ...................................................................................... 36 8.6.4 Write to Write ........................................................................................................................ 36 8.6.5 Concatenated Write Bursts ................................................................................................... 37 8.6.6 Non-Concatenated Write Bursts ........................................................................................... 37 8.6.7 Random Write Cycles ........................................................................................................... 38 8.6.8 Write to Read ....................................................................................................................... 38 8.6.9 Non-Interrupting Write to Read ............................................................................................. 38 8.6.10 Interrupting Write to Read .................................................................................................... 39 8.6.11 Write to Precharge ............................................................................................................... 39 8.6.12 Non-Interrupting Write to Precharge ..................................................................................... 39 8.6.13 Interrupting Write to Precharge ............................................................................................ 40 8.7 Precharge ........................................................................................................................................... 40 8.7.1 Precharge Command ........................................................................................................... 41 8.8 Auto Precharge .................................................................................................................................. 41 8.9 Refresh Requirements ........................................................................................................................ 41 8.10 Auto Refresh ...................................................................................................................................... 42 8.10.1 Auto Refresh Command ....................................................................................................... 42 8.10.2 Auto Refresh Cycles Back-to-Back ...................................................................................... 42 8.11 Self Refresh ........................................................................................................................................ 43 8.11.1 Self Refresh Command ........................................................................................................ 43 8.11.2 Self Refresh Entry and Exit .................................................................................................. 44 8.12 Power Down ....................................................................................................................................... 45 8.12.1 Power-Down Entry and Exit .................................................................................................. 45 8.13 Deep Power Down.............................................................................................................................. 46 8.13.1 Deep Power-Down Entry and Exit ........................................................................................ 46 8.14 Clock Stop .......................................................................................................................................... 47 8.14.1 Clock Stop Mode Entry and Exit ........................................................................................... 47 9. ELECTRICAL CHARACTERISTICS ................................................................................................................. 48 9.1 Absolute Maximum Ratings ................................................................................................................ 48 9.2 Input / Output Capacitance ................................................................................................................. 48 Publication Release Date: Jun. 04, 2018 Revision: A01-006 - 2 -