CY29940 2.5 V or 3.3 V, 200 MHz, 1:18 Clock Distribution Buffer 2.5 V or 3.3 V, 200 MHz, 1:18 Clock Distribution Buffer Features Functional Description 200 MHz clock support The CY29940 is a low-voltage 200 MHz clock distribution buffer with the capability to select either a differential LVPECL or a LVPECL or LVCMOS/LVTTL clock input LVCMOS/LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary LVCMOS/LVTTL compatible inputs system clock. All other control inputs are LVCMOS/LVTTL 18 clock outputs: drive up to 36 clock lines compatible. The eighteen outputs are 2.5V or 3.3V LVCMOS/LVTTL compatible and can drive 50 series or parallel 60 ps typical output-to-output skew terminated transmission lines. For series terminated Dual or single supply operation: transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:36. Low output-to-output 3.3 V core and 3.3 V outputs skews make the CY29940 an ideal clock distribution buffer for 3.3 V core and 2.5 V outputs nested clock trees in the most demanding of synchronous 2.5 V core and 2.5 V outputs systems. Pin compatible with MPC940L, MPC9109 For a complete list of related documentation, click here. Available in Commercial and Industrial temperature 32-pin TQFP package Block Diagram VDD VDDC PECL CLK 0 PECL CLK 18 Q0-Q17 1 TCLK TCLK SEL Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07283 Rev. *J Revised November 22, 2017CY29940 Pin Configuration VSS 1 24 Q6 VSS 2 23 Q7 TCLK 3 22 Q8 TCLK SEL 4 21 VDD PECL CLK 5 CY29940 20 Q9 PECL CLK 6 19 Q10 VDD 7 18 Q11 VDDC 8 17 VSS Pin Description 1 Pin Name PWR I/O Description 5 PECL CLK I, PU PECL input clock 6 PECL CLK I, PD PECL input clock 3 TCLK I, PD External reference/test clock input 9, 10, 11, 13, 14, Q(17:0) VDDC O Clock outputs 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32 4 TCLK SEL I, PD Clock Select Input. When LOW, PECL clock is selected and when HIGH TCLK is selected. 8, 16, 29 VDDC 3.3 V or 2.5 V power supply for output clock buffers 7, 21 VDD 3.3 V or 2.5 V power supply 1, 2, 12, 17, 25 VSS Common ground Note 1. PD = Internal Pull-Down, PU = Internal Pull-up Document Number: 38-07283 Rev. *J Page 2 of 10 Q17 9 32 Q0 Q16 10 31 Q1 Q15 11 30 Q2 VSS 12 29 VDDC Q14 13 28 Q3 Q13 14 27 Q4 Q12 15 26 Q5 VDDC 16 25 VSS