AS4C128M8D1-6TIN Revision History AS4C128M8D1-6TIN 66pin TSOP II PACKAGE Revision Details Date Rev 1.0 Initial Issue Dec. 2016 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice - 1 of 57 - Confidential Rev. 1.0 Dec. 2016AS4C128M8D1-6TIN Features Description - High speed data transfer rates with system frequency The AS4C128M8D1-6TIN is a four bank up to 166MHz DDR DRAM organized as 4 banks x 32Mbit x 8. The - Data Mask for Write Control AS4C128M8D1-6TIN achieves high speed data - Four Banks controlled by BA0 & BA1 transfer rates by employing a chip architecture that - Programmable CAS Latency: 2, 2.5, 3 pre-fetches multiple bits and then synchronizes - Programmable Wrap Sequence: Sequential the output data to a system clock. or Interleave All of the control, address, circuits are synchronized - Programmable Burst Length: with the positive edge of an externally supplied clock. I/O 2, 4, 8 for Sequential Type transactions are occurring on both edges of DQS. 2, 4, 8 for Interleave Type Operating the four memory banks in an interleaved - Automatic and Controlled Precharge Command fashion allows random access operation to occur at a - Power Down Mode higher rate than is possible with standard DRAMs. A - Auto Refresh and Self Refresh sequential and gapless data rate is possible - Refresh Interval: 8192 cycles/64 ms depending on burst length, CAS latency and speed - Available in 66 Pin TSOP II grade of the device. - SSTL-2 Compatible I/Os - Double Data Rate (DDR) - Bidirectional Data Strobe (DQS) for input and output data, active on both edges - On-Chip DLL aligns DQ and DQs transitions with CK transitions - Differential clock inputs CK and CK - VDD = 2.5V 0.2V, VDDQ = 2.5V 0.2V - tRAS lockout supported - Concurrent auto precharge option is supported Table 1. Ordering Information Part Number Org Temperature MaxClock (MHz) Package AS4C128M8D1-6TIN 128Mx8 Industrial -40C to +85C 166 66pin TSOPII Confidential - 2 of 57 - Rev. 1.0 Dec. 2016