AS4C128M8D3LA-12BIN Alliance Memory

AS4C128M8D3LA-12BIN AS4C128M8D3LA-12BCN Revision History AS4C128M8D3LA-12BCN/AS4C128M8D3LA-12BCN 78 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Sep. 201 6 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1/83 - Rev.1.0 Sep. 2016AS4C128M8D3LA-12BIN AS4C128M8D3LA-12BCN Features Overview JEDEC Standard Compliant The 1Gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed Power supplies: V & V = +1.35V DD DDQ operation. It is internally configured as an eight bank Backward compatible to V & V = 1.5V 0.075V DD DDQ DRAM. Operating temperature: The 1Gb chip is organized as 16Mbit x 8 I/Os x 8 Commercial: 0C to 95C (TC) bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to Industrial :-40C to 95C (TC) 1600 Mb/sec/pin for general applications. The chip is Supports JEDEC clock jitter specification designed to comply with all key DDR3L DRAM key Fully synchronous operation features and all of the control and address inputs are synchronized with a pair of externally supplied differential Fast clock rate: 800MHz clocks. Inputs are latched at the cross point of differential Differential Clock, CK & CK clocks (CK rising and CK falling). All I/Os are synchronized Bidirectional differential data strobe with differential DQS pair in a source synchronous - DQS & DQS fashion. 8 internal banks for concurrent operation These devices operate with a single 1.35V -0.067V 8n-bit prefetch architecture /+0.1V power supply and are available in BGA packages. Pipelined internal architecture Precharge & active power down Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control 8192 refresh cycles / 64ms - Average refresh period 7.8s -40C TC +85C 3.9s +85C TC + 95C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 78-ball 8 x 10.5 x 1.0mm FBGA package - Pb and Halogen Free Table 1. Ordering Information Temperature Max Clock (MHz) Product part No Org Package 800 AS4C128M8D3LA-12BCN 78-ball FBGA 128M x 8 Commercial 0C to 95C 800 AS4C128M8D3 LA-12BIN 78-ball FBGA 128M x 8 Industrial -40C to 95C Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t (ns) t (ns) RCD RP 13.75 13.75 800 MHz 11 DDR3 L-1600 Confidential - 2/83 - Rev.1.0 Sep. 2016