AS4C256M16D3B-12BIN AS4C256M16D3B-12BCN Revision History 4Gb AS4C256M16D3B - 12BIN/BCN 96 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Apr. 2016 Rev 1.1 Add Industrial part in datasheet Apr. 2017 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1/41 - Rev.1.1 April 2017AS4C256M16D3B-12BIN AS4C256M16D3B-12BCN Specifications Features - Density : 4G bits - Double-data-rate architecture two data transfers per clock - Organization : 32M words x 16 bits x 8 banks cycle - Package : - The high-speed data transfer is realized by the 8 bits - 96-ball FBGA prefetch pipelined architecture - Lead-free (RoHS compliant) and Halogen-free - Bi-directional differential data strobe (DQS and DQS) is - Power supply : VDD, VDDQ = 1.5V 0.075V transmitted/received with data for capturing data at the re- - Data rate : ceiver - 1600Mbps - DQS is edge-aligned with data for READs center-aligned - 2KB page size with data for WRITEs - Row address: A0 to A14 - Differential clock inputs (CK and CK) - Column address: A0 to A9 - DLL aligns DQ and DQS transitions with CK transitions - Eight internal banks for concurrent operation - Commands entered on each positive CK edge data and - Burst lengths (BL) : 8 and 4 with Burst Chop (BC) data mask referenced to both edges of DQS - Burst type (BT) : - Data mask (DM) for write data - Sequential (8, 4 with BC) - Interleave (8, 4 with BC) - Posted CAS by programmable additive latency for better - CAS Latency (CL) : 5, 6, 7, 8, 9, 10, 11 command and data bus efficiency - CAS Write Latency (CWL) : 5, 6, 7, 8 - On-Die Termination (ODT) for better signal quality - Precharge : auto precharge option for each burst access - Synchronous ODT - Driver strength : RZQ/7, RZQ/6 (RZQ = 240 ) - Dynamic ODT - Refresh : auto-refresh, self-refresh - Asynchronous ODT - Refresh cycles : - Average refresh period - Multi Purpose Register (MPR) for pre-defined pattern read 7.8 s at -40C Tc +85C out 3.9 s at +85C < Tc +95C - ZQ calibration for DQ drive and ODT - Operating case temperature range - Programmable Partial Array Self-Refresh (PASR) - Commercial Tc = 0C to +95C - RESET pin for Power-up sequence and reset function - Industrial Tc = -40C to +95C - SRT range : Normal/extended - Programmable Output driver impedance control Table 1. Ordering Information Part Number Org Temperature MaxClock (MHz) Package AS4C256M16D3B-12BCN 256Mx16 800 96-ball FBGA Commercial 0C to +95C AS4C256M16D3B-12BIN 256Mx16 800 96-ball FBGA Industrial -40C to +95C Table 2. Speed Grade Information Speed Grade CAS Latency tRCD (ns) tRP (ns) Clock Frequency DDR3-1600 800MHz 11 13.75 13.75 Confidential - 2/41 - Rev.1.1 April 2017