AS4C256M16D3LB-12BAN Revision History 4Gb AS4C256M16D3LB - 12BAN 96 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Mar. 2018 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1/46 - Rev.1.0 Mar 2018AS4C256M16D3LB-12BAN Specifications Features - Density : 4G bits - Double-data-rate architecture two data transfers per clock - Organization : 32M words x 16 bits x 8 banks cycle - Package : - The high-speed data transfer is realized by the 8 bits - 96-ball FBGA prefetch pipelined architecture - Lead-free (RoHS compliant) and Halogen-free - Bi-directional differential data strobe (DQS and DQS) is - Power supply : VDD, VDDQ = 1.35V (1.283V to 1.45V) transmitted/received with data for capturing data at the re- - Backward compatible to VDD, VDDQ = 1.5V 0.075V ceiver - Data rate : - DQS is edge-aligned with data for READs center-aligned - 1600Mbps with data for WRITEs - 2KB page size - Differential clock inputs (CK and CK) - Row address: A0 to A14 - DLL aligns DQ and DQS transitions with CK transitions - Column address: A0 to A9 - Commands entered on each positive CK edge data and - Eight internal banks for concurrent operation data mask referenced to both edges of DQS - Burst lengths (BL) : 8 and 4 with Burst Chop (BC) - Data mask (DM) for write data - Burst type (BT) : - Sequential (8, 4 with BC) - Posted CAS by programmable additive latency for better - Interleave (8, 4 with BC) command and data bus efficiency - CAS Latency (CL) : 5, 6, 7, 8, 9, 10, 11 - On-Die Termination (ODT) for better signal quality - CAS Write Latency (CWL) : 5, 6, 7, 8 - Synchronous ODT - Precharge : auto precharge option for each burst access - Dynamic ODT - Driver strength : RZQ/7, RZQ/6 (RZQ = 240 ) - Asynchronous ODT - Refresh : auto-refresh, self-refresh - Multi Purpose Register (MPR) for pre-defined pattern read - Refresh cycles : - Average refresh period out 7.8 s at -40C Tc +85C - ZQ calibration for DQ drive and ODT 3.9 s at +85C < Tc +105C - Programmable Partial Array Self-Refresh (PASR) - Operating case temperature range - RESET pin for Power-up sequence and reset function Automotive Tc = -40C to +105C - SRT range : Normal/extended - Programmable Output driver impedance control Table 1. Ordering Info rmation Part Number Org Temperature MaxClock (MHz) Package Automotive AS4C256M16D3 LB-12BAN 256Mx16 800 96-ball FBGA -40C to 105C Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t (ns) t (ns) RCD RP 13.75 13.75 800 MHz 11 DDR3L-1600 Confidential - 2/46 - Rev.1.0 Mar 2018