AS4C256M8D3LC-12BIN Alliance Memory

AS4C256M8D3LC Revision History 2Gb AS4C 256M8D3LC 78 ball FBGA PACKAGE Revision Details Date Rev 1.0 Initial Release Nov.2020 ALLIANCE MEMORY Inc. reserves the right to change products or specification without notice. 12815 NE 124th Street Suite D, Kirkland, WA 98034 USA Main +1(425)868-4456 Fax:+1 (425)898-8628 Confidential - 1 of 87 - Rev.1.0. Nov. 2020 AS4C256M8D3LC 256M x 8 bit DDR3L Synchronous DRAM (SDRAM) Advance (Rev. 1.1, Jun. /2020) Features Overview JEDEC Standard Compliant The 2Gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed Power supplies: V & V = +1.35V (1.283V~1.45V) DD DDQ operation. It is internally configured as an eight bank Backward compatible to V & V = +1.5V 0.075V DD DDQ DRAM. Operating temperature: The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 bank : T = 0~95 C - Commercial C devices. These synchronous devices achieve high - Industrial : T = -40~95 C C speed double-data-rate transfer rates of up to 1600 Mb/ Extended temperature : Tc = 85~95C - sec/pin for general applications. Supports JEDEC clock jitter specification The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address Fully synchronous operation inputs are synchronized with a pair of externally supplied Fast clock rate: 800MHz differential clocks. Inputs are latched at the cross point Differential Clock, CK & CK of differential clocks (CK rising and CK falling). All I/Os Bidirectional differential data strobe are synchronized with differential DQS pair in a source - DQS & DQS synchronous fashion. 8 internal banks for concurrent operation 8n-bit prefetch architecture Pipelined internal architecture Precharge & active power down Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control Average refresh period - 8192 cycles/64ms (7.8us at -40C T +85C) C - 8192 cycles/32ms (3.9us at +85C T +95C) C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 78-ball 7.5 x 10.5 x 1.0mm FBGA package - Pb and Halogen Free Table 1. Ordering Information Temperature Max Clock (MHz) Product part No Org Package AS4C 256M8D3LC-12BCN 256M x 8 Commercial 0C to 95C 800 78-ball FBGA Industrial -40C to 95C AS4C 256M8D3LC-12BIN 256M x 8 800 78-ball FBGA Table 2. Speed Grade Information Clock Frequency Speed Grade CAS Latency t t (ns) (ns) RP RCD 11 13.75 800MHZ DDR3 L-1600 13.75 Confidential - 2 of 87 - Rev.1.0. Nov. 2020