AS4C64M16D2A-25BINTR

AS4C64M16D2A-25BIN AS4C64M16D2A-25BCN Revision History 1Gb AS4C64M16D2A 4 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Apr. 2017 Rev 1.1 Amend table 26 & table 27 test conditions Oct. 2017 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Rev.1.1 October 2017 Confidential - 1 of 62 -AS4C64M16D2A-25BIN AS4C64M16D2A-25BCN 64M x 16 bit DDRII Synchronous DRAM (SDRAM) Advance (Rev. 1. 1, Oct. /201 7) Features Overview JEDEC Standard Compliant The AS4C64M16D2A is a high-speed CMOS Double- Data-Rate-Two (DDR2), synchronous dynamic random JEDEC standard 1.8V I/O (SSTL 18-compatible) - access memory (SDRAM) containing 1024 Mbits in a Power supplies: V & V = +1.8V 0.1V DD DDQ 16-bit wide data I/Os. It is internally configured as a 8- Operating temperature: bank DRAM, 8 banks x 8Mb addresses x 16 I/Os. The Commercial temperature: TC = 0~85 C device is designed to comply with DDR2 DRAM key Industrial temperature: TC = -40~95 C features such as posted CAS with additive latency, Write latency = Read latency -1, Off-Chip Driver (OCD) Supports JEDEC clock jitter specification impedance adjustment, and On Die Termination(ODT). Fully synchronous operation Fast clock rate: 400 MHz All of the control and address inputs are synchronized Differential Clock, CK & CK with a pair of externally supplied differential clocks. Bidirectional single/differential data strobe Inputs are latched at the cross point of differential clocks - DQS & DQS (CK rising and CK falling) All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS ) in a 8 internal banks for concurrent operation source synchronous fashion. The address bus is used to 4-bit prefetch architecture convey row, column, and bank address information in Internal pipeline architecture RAS , CAS multiplexing style. Accesses begin with Precharge & active power down the registration of a Bank Activate command, and then it Programmable Mode & Extended Mode registers is followed by a Read or Write command. Read and Posted CAS additive latency (AL): 0, 1, 2, 3, 4, 5,6 write accesses to the DDR2 SDRAM are 4 or 8-bit burst oriented accesses start at a selected location and WRITE latency = READ latency - 1 t CK continue for a programmed number of locations in a Burst lengths: 4 or 8 programmed sequence. Operating the eight memory Burst type: Sequential / Interleave banks in an interleaved fashion allows random access DLL enable/disable operation to occur at a higher rate than is possible with Off-Chip Driver (OCD) standard DRAMs. An auto precharge function may be - Impedance Adjustment enabled to provide a self-timed row precharge that is - Adjustable data-output drive strength initiated at the end of the burst sequence. A sequential and gapless data rate is possible depending on burst On-die termination (ODT) length, CAS latency, and speed grade of the device. RoHS compliant Auto Refresh and Self Refresh 8192 refresh cycles / 64ms - Average refresh period 7.8s -40 C TC +85 C 3.9s +85 C TC +95 C 84-ball 8 x 12.5 x 1.2mm (max) FBGA package - Pb and Halogen Free Table 1. Ordering Information Part Number Org Temperature MaxClock (MHz) Package AS4C64M16D2A-25BCN 400 MHz 64Mx16 Commercial 0C to +85C 84-ball FBGA AS4C64M16D2A-25BIN Industrial -40C to +95C 400 MHz 64Mx16 84-ball FBGA Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency tRCD (ns) tRP (ns) DDR2-800 5 12.5 12.5 400 MHz Rev.1.1 October 2017 Confidential - 2 of 62 -