AS4C64M16D3A-12BCN Alliance Memory

AS4C64M16D3A-12BIN AS4C64M16D3A-12BCN Revision History AS4C64M16D3A-12BCN/AS4C64M16D3A-12BIN 96 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Aug. 2016 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1/86 - Rev.1.0 Aug.2016AS4C64M16D3A-12BIN AS4C64M16D3A-12BCN Features Overview JEDEC Standard Compliant The 1Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. It is Power supplies: V & V = +1.5V 0.075V DD DDQ internally configured as an eight bank DRAM. Operating temperature: The 1Gb chip is organized as 8Mbit x 16 I/Os x 8 Commercial: 0C to 95C (TC) bank devices. These synchronous devices achieve Industrial :-40C to 95C (TC) high speed double-data-rate transfer rates of up to 1 600 Mb/sec/pin for general applications. Supports JEDEC clock jitter specification The chip is designed to comply with all key DDR3 Fully synchronous operation DRAM key features and all of the control and address Fast clock rate: 800MHz inputs are synchronized with a pair of externally Differential Clock, CK & CK supplied differential clocks. Inputs are latched at the Bidirectional differential data strobe cross point of differential clocks (CK rising and CK - DQS & DQS falling). All I/Os are synchronized with differential DQS 8 internal banks for concurrent operation pair in a source synchronous fashion. These devices operate with a single 1.5V 0.075V 8n-bit prefetch architecture power supply and are available in BGA packages. Pipelined internal architecture Precharge & active power down Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control 8192 refresh cycles / 64ms - Average refresh period 7.8s -40 TC +85 3.9s +85 TC +95 Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 96-ball 8 x 13 x 1.0mm FBGA package - Pb and Halogen Free Table 1. Ordering Information Temperature Org Max Clock (MHz) Product part No Package 800 AS4C64M16D3A-12BCN 64M x 16 Commercial 0C to 95C 96-ball FBGA 800 AS4C64M16D3A-12BIN 64M x 16 Industrial -40C to 95C 96-ball FBGA Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t (ns) t (ns) RCD RP 13.75 13.75 DDR3-1600 800 MHz 11 Confidential - 2/86 - Rev.1.0 Aug.2016